In this thesis we present an FPGA software/hardware co-design for the CABAC decoder. CABAC is the Context-based Adaptive Binary Arithmetic Coding used in the H.264/AVC video standard. This standard gives better compression effciency, but with greater complexity and implementation cost. A large part of this cost comes from the CABAC entropy coding. The CABAC coding has a tight feedback loop between the binary arithmetic coding stage and the context modeler stage of the coding process. This means that the video stream has to be coded in a sequential way. We attempt acceleration of the CABAC decoding process in a fashionable way on dedicated programmable hardware. An FPGA implementation of the CABAC entropy decoding process is used in co-operation with the decoding software on a Xilinx Virtex 4 platform. Actual synthesis results show that our approach results in a fast and compact implementation, targeted at the state-of-the-art FPGA devices.