NoCs have been considered as the new design paradigm for large MPSoC systems in the past ten years. In the beginning NoCs were radically different compared to the current state of the art mainly due to the unexpected unique challenges that system designers had to solve with the evolving CMOS technology. In fact, various hidden physical level issues may potentially degrade system performance, exceed the available power budgets or even endanger the overall design feasibility. The connectivity among different multi-core elements is such an issue that has to be addressed during the design of the overall communication infrastructure. Two different classes of implications related to the aggressive CMOS technology scaling, resulting in growing process variations, reduced power budgets per unit area and worsening signal integrity on chip, have to be considered. On one hand, a good topology is required to provide adequate sub-system connectivity while also satisfying the bandwidth and performance requirements. On the other hand, increasing synchronization issues make the system design difficult and in some cases even impossible to be realized under a rigid synchronization model. For instance, the topology strongly depends on the physical effects as consequence of the wire delay reverse scaling while the synchronization issues are tightly related to process variation effects. Therefore, in the current and the future CMOS technology nodes, ad-hoc counter measures must be adopted to cope with the above problems. In this thesis we propose a system-level analysis framework and design methodology both considering real layout effects. Our analysis is not only limited to classical layout effects such as the non-regularity of a rectangular tile; the real wire delays of inter-switch links; the number of pipeline stages required to provide the requested link performance; the maximum tolerated skew of a certain synchronization scheme; and more. We also consider the implications of the above physical phenomena while re-designing our architectural blocks. The ultimate result is a framework which is truly technology aware, ready to meet the challenges of the future CMOS technology landscape.