ASML is a world leading supplier of complex lithography machines for the semiconductor industry. A lithography machine consists of many subsystems, e.g., Light Source, Lens, Reticle handler, Reticle stage, Wafer handler and Wafer stage, which synchronize together to make the machine work. The Reticle stage holds the circuit pattern, also known as reticle and the Wafer stage module holds the wafer. The UV light from the light source is projected on the circuit pattern, which is then passed through the lens to imprint the pattern on the wafer. Since the circuit pattern has to be imprinted on the wafer, the movement of the modules; Reticle stage and Wafer stage should be synchronized in six degrees of freedom (DoF) with nanometer accuracy. To employ the movement of the subsystems, motion controllers are used in ASML, and Long Stroke and Short Stroke controllers are responsible for the movement of a part of the Wafer stage subsystem. It has been envisioned that future lithography machines, because of its high precision mechatronic requirements, will need motion control algorithms, that run at higher sampling frequencies with a severely reduced IO latency budget. Current hardware architectures will not be able to meet the demands of these future motion control algorithms. In this thesis, we propose an architecture, that uses a multi-ASIP in FPGA as an accelerator in conjunction with a CPU, which acts as a master to run the motion control applications. The proposal of using multi-ASIP FPGA in conjunction with CPU is based on the analysis carried out previously in ASML. It was observed that a sampling frequency exceeding 100 KHz can be obtained after deploying the Long Stroke controller and Short Stroke controller on a multi-ASIP platform in FPGA. However, this work considered only the data flow and not the supervisory control. After carrying out detailed analysis, we could predict that a sampling frequency of 40 KHz could be achieved by offloading the compute intensive blocks present in the Long Stroke and Short Stroke controller from the CPU to FPGA. The sampling frequency of 40 KHz can be achieved by considering, both the data flow and supervisory control, and the communication between the CPU and FPGA. Finally, after offloading the compute intensive blocks from the CPU on the multi-ASIP FPGA, and after implementing the data flow and supervisory control and communication mechanism between the CPU and FPGA, we can justify that the sampling frequency of 40 KHz can be achieved.