The bandgap limitation of silicon (Si) limits the imaging capabilities of conventional Si CMOS Image Sensors to wavelengths below 1100 nm and thus are inadequate for near-infrared (NIR) / short-wave infrared (SWIR) imaging applications such as metrology, medical imaging and computer vision. Current SWIR image sensors, while capable of detecting wavelengths up to 2000 nm, suffer from several critical drawbacks: they are incompatible with CMOS technology, lack the scalability inherent to CMOS processes, and are prohibitively expensive.

This thesis presents the design and simulation of a CMOS-compatible microstructured germanium-on-silicon (Ge-on-Si) visible and SWIR wideband image sensor. The proposed design uses light-trapping microstructures on the sensor's surface to help enhance the optical efficiency of the infrared-sensitive germanium layer while maintaining compatibility with standard CMOS fabrication techniques. The proposed design is highly scalable, with diffusion-drift and finite-difference time-domain (FDTD) simulations of pixels with 5 um, 15 um and 55 um pitches demonstrating a quantum efficiency of 28% at 1000 nm and 2% at 1300 nm using only a 100 nm Ge layer while also being compatible with the 4T-pixel active pixel sensor (APS) architecture. With future developments using 1 µm Ge layer potentially allowing for QE over 40% across the entire visible+NIR/SWIR spectrum, such a design will enable integrated wideband integrated imaging applications that can utilize the developments of existing CMOS image sensors.

In various metrological imaging applications, such as astronomical studies and medical applications, the incident illumination from the image is focused densely on certain regions of the image and sparsely spread over others. Ideally, the sensor's pixels have high spatial resolution at regions of interest to provide high resolution and distinguish features of the image. Similarly, larger, low-resolution pixels are preferred in regions of sparsely distributed information.

As pixel readouts form a significant portion of an image sensor's power budget, larger low-power pixels should dominate the background locations to lower the number of readouts and power consumption. Since different applications may have different regions tending to dense and sparse incidence, the presence of high-resolution and low-resolution pixels should be configurable. This work aims to research an image sensor whose spatial resolution is configurable at different locations on the chip.

The primary goal of this thesis work is:
To create a CMOS-based image sensor named FlexCAM with adaptable (by utilizing control gates and proper biasing schemes) resolution modes for:
a) High spatial resolution at regions of interest where the signal is dense. Here, each pixel is read through its amplifier
b) Low spatial resolution at regions where the signal is sparse, utilizing charge binning onto a focal pixel. Here, only the amplifier of the focal pixel is activated, thus reducing power consumption.
Additionally, this thesis will include the optical and electrical design trade-offs, the design of the foundry process flow, and details of the proposed experimental setup. The work also provides preliminary simulations for proof-of-concept for both resolution modes.