CJ

C. Ji

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Trace-based P4 Program Generation

While the adoption of programmable data planes is increasing, writing correct and efficient P4 programs remains a challenging and error-prone process. This hinders the rapid development of custom in-network functionality and limits the accessibility of data-plane programming to a small set of experts. In this paper, we present T4G, a system that automatically synthesizes P4 programs from network behavior expressed as input-output network traces. Unlike prior approaches that rely on high-level abstraction or domain-specific languages, T4G operates with example packet captures, eliminating the need for manual abstraction or rule specifications from network operators. T4G introduces a novel input-output grouping technique that identifies logical packet transformation behavior from packet traces, and performs a divide-and-conquer synthesis that scales to complex forwarding logic. Our experimental results show the ability of T4G to generate different types of programs and demonstrate the potential of T4G in generating complex P4 programs. ...
Doctoral thesis (2026) - C. Ji, F.A. Kuipers, K.G. Langendoen
Communication networks have become an essential part of the critical infrastructure of modern society, supporting cloud computing, online services, financial systems, entertainment, large language model services, and many other applications. As these services and applications become increasingly latency-sensitive, distributed, and availability-critical, networks are expected to provide more than just packet forwarding services. Modern networks must support flexible packet-processing behavior, adapt quickly to changing network conditions, and maintain reliable operations.

For decades, packet forwarding was mainly performed by fixed-function routers and switches. These devices provide high performance, yet their packet processing behavior is largely constrained by the underlying hardware and vendor-specific interfaces. SDN improved network flexibility by making the control plane programmable, yet many time-sensitive decisions still require communication between the data plane and the controller. More recently, programmable data-plane devices have shifted part of this flexibility into the forwarding plane, allowing network operators to define packet-processing behaviors directly using programming languages such as P4. Such programmability enables parsing custom headers, implementing match-action logic, and, crucially, maintaining custom stateful logic at line rate.

Among the capabilities exposed by programmable data-plane devices, operator-defined stateful packet processing is one of the most important features. While fixed-function devices have supported specific forms of stateful behavior, such as counters, meters, and protocol-specific state tables, programmable data planes allow operators to define how packets interact with locally maintained state. This enables packet-processing decisions to depend not only on the current packet, but also on flow history, network context, and other factors. As a result, programmable data-plane devices can support advanced in-network applications, including load balancing, in-band telemetry, security, and in-network computation.

However, statefulness also makes programmable data planes difficult to construct, update, and protect. A stateful data-plane application is not merely defined by the program logic, but also by the state it creates and maintains. This state may change at line rate under tight hardware constraints; thus, building practical stateful data-plane applications requires mechanisms for automation and resilience.

This thesis investigates how programmable switches can support automation and resilience for stateful data-plane applications. The core idea is that data-plane state must be managed explicitly throughout the data-plane application life cycle, so that it can be constructed, preserved, and used correctly.

The systems developed in the thesis follow three connected directions. First, the thesis examines how program construction and evolution can be simplified to reduce the manual effort required by network operators. Second, the thesis studies how stateful data-plane applications can remain available in the presence of link or device failures. Third, the thesis explores how locally maintained states can support collaborative security applications, where multiple programmable devices jointly contribute to a network-wide decision.

The contributions of this thesis show that programmable stateful packet processing requires more than exposing packet logic to operators. State management, failure handling, and application logic must be considered jointly to make stateful behavior practical in programmable data planes. ...

An Adaptive Resilient Data-Plane for Stateful Packet Processing

Conference paper (2026) - Chenxing Ji, Adrian Zapletal, Fernando Kuipers
Stateful network functions on programmable switches make decisions within microseconds by directly operating on in-switch state. However, their performance hinges on the availability and correctness of the state stored in scarce on-chip memory. When a switch failure occurs, fast reroute can restore connectivity, but the rerouted traffic loses access to the existing state, causing incorrect network behavior. In extreme cases, packets may no longer be forwarded. Given switch constraints and bandwidth overhead, maintaining synchronous backups of all states across all nodes is practically infeasible. Moreover, existing recovery mechanisms typically incur high latency. In this paper, we present ARDAPL, a framework that leverages unallocated hardware resources to achieve in-data-plane failover at the μs-scale. We have prototyped ARDAPL on Tofino switches and evaluated its impact on existing traffic. Our experimental results show that less than 0.002% of traffic was affected over the entire failure period, and ARDAPL can achieve sub-50μs failover time while incurring 5μs latency. ...
Conference paper (2025) - C. Ji, F. Kuipers
Programmable data plane devices have enabled various in-network applications that rely on locally stored state for delivering low-latency and high-throughput services. However, these applications are susceptible to network failures, which can disrupt state access and network functionality. Timely and reliable failure detection is therefore a critical component of a stateful data plane. In this paper, we propose a data plane framework, FASTR, that enables microsecond-scale fast failure detection between directly connected switches. FASTR can achieve sub- 10 μ s detection latency by implementing a heartbeat mechanism in the data plane. In addition, FASTR also incorporates traffic-awareness to reduce overhead and priority queuing to avoid false alarms. We validate FASTR with hardware experiments, demonstrating that it can consistently detect failures within 10 μ s using a 4 μ s interval while remaining robust to network congestion. ...
Conference paper (2025) - E. Bardhi, C. Ji, A. Imran, M. Shahbaz, R. Lazzeretti, M. Conti, F. Kuipers
The emergence of softwarized network devices, like programmable switches and smart NICs, has brought about new and advanced network functionalities. Intelligent decision-making becomes possible at line rate by offloading network functionality from the network control-plane to the programmable data-plane. In this paper, we offload fine-grained Distributed Denial of Service (DDoS) attack detection to the data-plane. The state-of-the-art in this regard, mainly aims to embed Machine Learning (ML) models into the data-plane without compromising on inference accuracy. Besides accuracy, we must consider multiple other factors, like traffic feature availability and false positive rates. To that end, we propose O’MINE: ONE MODEL IS NOT ENOUGH, a novel collaborative detection mechanism comprising lightweight ML models. This maximises the detection accuracy while keeping the false positive rate (FPR) low. We use three state-of-the-art datasets to evaluate the O’MINE algorithm and its ML models. Our results show that O’MINE can detect DDoS attacks with high accuracy (≈98% and ≈96% with full and scarce training data, respectively) and low FPR (≈0.22% and ≈0.72% with full and scarce training data, respectively), outperforming the state-of-the-art. Lastly, O’MINE only consumes a few device resources (≈6% of LUT and ≈4% of FF) on the Xlinx Alevo U250 FPGA we have used for inference at line rate. ...
Conference paper (2023) - C. Ji, F.A. Kuipers
To cater to constantly changing network needs, enabling stateful reconfiguration of Network Functions (NFs) is crucial. Recently, there has been growing interest in offloading NFs to programmable network devices. Unfortunately, it is currently not possible to maintain the full state of NFs during a switch reconfiguration without consuming network resources from and to neighboring switches. In this paper, we present State4, a framework that maintains the state of P4 programs during the reconfiguration of a P4-programmab1e network device, by only using a small amount of local resources on the switch undergoing reconfiguration. State4 acts on both the in-switch control-plane and the data-plane. By utilizing the in-switch local controller, State4 requires no external network resources to achieve reconfiguration while preserving states. As such, State4 enables on-The-fly reconfiguration of stateful NFs, at minimal traffic disruption, where previously traffic had to be re-routed. ...