B. Turkovic
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9 records found
1
In this paper, we take a fundamentally different approach, called P4QoS, by embedding QoS requirements in the packets themselves and leveraging P4-programmable network switches to process the traffic based on them. We illustrate and evaluate our approach with latency as our QoS metric, but our concept can be applied to other metrics as well. Our evaluation, both in software (Mininet) and in hardware (Intel Tofino), shows that P4QoS can satisfy application-specific QoS requirements with negligible memory overhead. ...
In this paper, we take a fundamentally different approach, called P4QoS, by embedding QoS requirements in the packets themselves and leveraging P4-programmable network switches to process the traffic based on them. We illustrate and evaluate our approach with latency as our QoS metric, but our concept can be applied to other metrics as well. Our evaluation, both in software (Mininet) and in hardware (Intel Tofino), shows that P4QoS can satisfy application-specific QoS requirements with negligible memory overhead.
The concept of network slicing enables operators to provision multiple virtual networks on top of a single (shared) physical infrastructure. Adding elasticity to slicing, i.e., the ability to on-demand provision/release dedicated network resources, improves resource utilization. However, efficiently allocating and scaling slice resources, while maintaining state consistency, is challenging. Especially with P4-programmab1e network devices that process packets at Tbps speeds, controller-driven scaling of network functions would be too time-consuming, and data-plane scaling is needed. In this paper, we address this need, by developing a custom scaling protocol and framework that can consistently, with negligible delay, scale network slices and functions transparently to the slice end-users. We compare, via emulation and experiments on programmable hardware, our approach to state-of-the-art scaling techniques and demonstrate significant slice resource utilization improvements and scaling duration reductions.
F1ows that have exceeded a given percentage of the last sliding window of N packets, denoted as heavy-hitter flows, require special handling, since they may disrupt the service of other flows or may be indicative of malicious traffic. However, even when equipped with a programmable switch, it is unclear how to detect heavy hitters on a per-packet basis, while obeying the stringent switch memory access rates. For instance, existing solutions, such as HashPipe, cannot detect heavy hitters without halving the line rate and do not support sliding windows. To the best of our knowledge, this paper is the first to present heavy-hitter detection solutions that provide per-packet granularity at line-rate performance. We realize this by introducing (1) Modulo sketching, a novel counting algorithm that reuses counters and limits the impact of smaller flows beyond early processing stages; and (2) Sequential Zeroing, a new approach to extending interval-based schemes to sliding window measurements. Our solutions are extensively evaluated, both via simulations and experiments on a Netronome SmartNIC, and demonstrate significant performance gains over the state-of-theart.
specific situations. However, their interactions and co-existence has, to date, not been thoroughly evaluated, which is the focus of this paper. Through head-to-head comparisons of loss-based, delay-based and hybrid types of congestion control algorithms, we reveal that fairness in resources claimed is often not achieved,
especially when flows sharing a link have different round-trip times or belong to different groups.
...
specific situations. However, their interactions and co-existence has, to date, not been thoroughly evaluated, which is the focus of this paper. Through head-to-head comparisons of loss-based, delay-based and hybrid types of congestion control algorithms, we reveal that fairness in resources claimed is often not achieved,
especially when flows sharing a link have different round-trip times or belong to different groups.
In this paper, we develop congestion avoidance methods that harness the power of fully programmable data-planes. The corresponding programmable switches, through languages such as P4, can be programmed to gather and react to important packet meta-data, such as queue load, while the data packets are being processed. In particular, we enable P4 switches to (1) track processing and queuing delays of latency-critical flows and (2) react immediately in the data-plane to congestion by rerouting the affected flows. Through a proof-of-concept implementation in emulation and on real hardware, we demonstrate that a data-plane approach reduces average and maximum delay, as well as jitter, when compared to non-programmable approaches. ...
In this paper, we develop congestion avoidance methods that harness the power of fully programmable data-planes. The corresponding programmable switches, through languages such as P4, can be programmed to gather and react to important packet meta-data, such as queue load, while the data packets are being processed. In particular, we enable P4 switches to (1) track processing and queuing delays of latency-critical flows and (2) react immediately in the data-plane to congestion by rerouting the affected flows. Through a proof-of-concept implementation in emulation and on real hardware, we demonstrate that a data-plane approach reduces average and maximum delay, as well as jitter, when compared to non-programmable approaches.