As CMOS feature size vertiginously approaches atomic limits, high leakage and power density and exacer-bating IC production costs are prompting for development of new materials, devices, beyond von-Neumann architectures and computing paradigms. Within this context, graphene has emerged as a promising post-Si front runner, owing to its remarkable properties. In this paper, we propose a generic graphene-based complementary-style Boolean gate structure with memory-lock, that allows logic and non-volatile memory co-location. The gate with memory-lock is composed of 2 cells - a pull-up cell performing the gate Boolean function and a pull-down cell performing the inverted Boolean function. Each cell in turn, has a graphene logic layer that carries out Boolean gates computation, and a graphene memory layer for storing the logic state of the gate. As simulation vehicle we considered an inverter gate with memory-lock. Simulation results indicate a current ratio of write/read to/from memory of 1.64.10²for gate input low, and of 2.55. 10²for gate input high. Furthermore, the inverter with memory-lock exhibits a 128× smaller area footprint when compared to the traditional physically separate logic (e.g., 7nm inverter gate) and memory (e.g., 7nm 6T SRAM cell), establishing the potential of proposed structure with memory-lock for more compact and energy efficient future beyond CMOS nano-electronic implementations, and making it highly promising for high-density computations.

In this paper we propose a generic graphene-based Spiking Neural Network (SNN) architecture for pattern recognition and the associated weight values initialization methodology. The SNN has a Winner-Takes-All 3-layer structure and exhibits tuneable recognition accuracy by exploiting interpatterns similarity/dissimilarity. To demonstrate the capabilities of our proposal we present an SNN instance tailored for low resolution MNIST handwritten digits recognition and evaluate its recognition accuracy by means of SPICE simulations. 2 voltage levels are initially utilized for synaptic weight values representation and the recognition accuracy varies from 75.8% to 99.2%, which, together with its compactness and energy efficient (pJ range/spike), suggests that our approach has great potential for edge device implementations.

The realization of energy efficient, low area, and fast processing neuron and synapse circuits is of prime importance for unleashing neuromorphic computing full potential. In this paper, we introduce a graphene-based synapse, which can emulate Spike Timing Dependent Plasticity (STDP) and Short/Long Term Plasticity (STP/LTP) with variable signal amplitude and temporal dynamics. The synapse operation is validated by means of SPICE simulations, and its synaptic modulation ability is showcased through reinforcement learning within a Spiking Neural Network for robotic navigation with obstacles avoidance. Besides its functional versatility, the proposed graphene-based synapse can potentially occupy low active area (≈ 170nm2) and operate at low voltage (200 mV ). When compared with a biological brain synapse, its energy consumption per spike for a weight update operation (0.5 fJ ) is 20 × - lower, while the processing speed is increased by six orders of magnitude. Such properties are essential desiderata for the realization of large scale neuromorphic systems, making the proposed graphene-based synapse an outstanding candidate for this purpose.