The current COVID-19 pandemic shows the necessity of personal protective equipment and face masks. In the project, a filter module with an in-situ ultraviolet-sterilization technique is designed that can serve as a new kind of smart personal protective equipment (SPPE). This technique is not used in wearable devices as of yet. The project thus aims to take the next step into the future of facemasks. The complete SPPE design is split into three submodules. In this thesis, the Sensing and Control submodule is designed. The Sensing and Control submodule is divided into three parts as well. In the first part of the design, a negative feedback control loop is developed. A photodiode transimpedance amplifier circuit provides the feedback, and the controller is programmed on a microcontroller. The control parameters are derived from a model in Simulink. In the second part of the design, the temperature and relative humidity are measured to transform the control loop’s reference value into a reference function. In the third part of the design, an estimation of the filter state of health is made by measuring the pressure drop over the filter material. Additionally, the airflow in the SPPE is calculated using equations from fluid mechanics to set the maximum allowable pressure drop. At the end of the thesis, the Sensing and Control submodule allows the SPPE to measure environmental conditions, control the ultraviolet intensity accordingly, and indicate if the filter requires replacement. The design is finalized with printed circuit board designs and an algorithm. With the design of the Sensing and Control submodule, the next step is taken towards the future of face masks.

Most current proximity sensing methods fail the stringent requirements of modern smartphones. A position-sensing device (PSD) requires a laser placed some distance away from the sensor, intensity-based solutions are sensitive to changes in reflectivity, and ultrasound-based sensors cannot measure small distances because of resonance. With modern transistors getting smaller and smaller, single-photon detectors have become feasible. Using a single-photon detector called a SPAD and a laser, the travel time of light can be measured. This technique, called time-of-flight, existed for several decades where radar and ultrasound are concerned but only recently includes single-photon detectors. Several products exist that use single-photon time of flight to measure proximity. However, they are limited in terms of maximum distance, resolution and ambient light tolerance. The question arises what the best possible performance of such a system is. For radar and ultrasound, this has been calculated long ago already, but for time of flight, no such analysis exists. This analysis is the main contribution of this thesis. A formula is calculated that takes all parameters of the system into account and produces an expected standard error. This formula is verified using a simulator. The effect of an increasing opening angle of laser and SPAD is analyzed, as well as different waveforms of the laser, using multiple SPADs in smart ways, and increasing the time of a single measurement. It is shown that when less than a thousand SPADs are used, no smart way of combining hits on different SPADs exists. The waveform emitted by a laser is typically a mix of a sine, a square wave and some effects resembling RC-behavior. The nearer to a square wave this is, the smaller the resulting standard error is. The most power-hungry aspect of such a proximity sensing solution is often the time discretization device. To obtain a high resolution in the order of millimeters, the time resolution should be in the order of picoseconds. Such an extremely high resolution, below the switching time of a single transistor, can typically only be obtained by trading trade area, power and read-out time for resolution. This thesis analyzes a solution using a low-resolution time-to-digital converter (TDC) and multiple sub-intervals for a shorter time to increase resolution.

This thesis details the design of a selection operator used in a Genetic Algorithm. The Genetic Algorithm is used for loudspeaker filter design of three way loudspeakers for which tournament selection was chosen as selection operator. A methodology is proposed and used to tune the parameters of tournament selection, which is based on diversity and fitness of the population. Besides basic tournament selection, two new adaptive selection operators based on tournament selection are proposed to improve its functionality. The first adaptive selection operator uses noise proportional to the fitness variance of the population to improve the efficiency of the genetic algorithm. The second adaptive selection operator uses a convergence stage to speed up the convergence towards the optimal filter. After the presented tuning process in this thesis, the latter adaptive selection operator was found to perform better. The optimal selection operator and parameters found in this thesis will not translate to every application, because they heavily depend on the design and the application of the genetic algorithm. However, the presented comparison of selection operators, the provided performance metrics and design methodology can still be used to guide the choice and the tuning process of a selection operator used in any genetic algorithm.

This paper reports the design of a part of a genetic algorithm, which is made to design analog filters for loudspeakers. The part in this report is the part which deals with the representation of electrical filter circuits, the mutation of these filters, and finding their transfer function. The considered representations are graph coding and a tree data structure. They are compared on intuitiveness, how well mutations can be performed, and the complexity of calculating the transfer function. The tree structure is reasoned to be the most suitable. Described is which mutations can be performed on a filter by the final program, as well as how embryo circuits are made, how the transfer function is calculated, and which hyperparameters were designed and how they were set. Finally, the design is implemented using Python and the operations are tested.

Mobile robots need to be fully autonomous in order to perform their tasks inside their environment. To do that, robots need to have an understanding of their environment, so that they can successfully localize and navigate themselves within it. The understanding of the robots' environment is created by solving the SLAM (Simultaneous Localization And Mapping) problem. The SLAM problem is usually approached using probabilistic laws; both the robot's path and the environment are estimated and represented by probability distributions. The estimate of the environment is incorporated into a map, which could either be one global map or a network of smaller connected local maps. In small areas where the sensors' errors and inaccuracies remain low, the creation of one global map is preferred. However, as the area grows larger, the global map becomes inaccurate due to accumulated errors. Therefore the strategy of creating a network of local maps is employed. Even though this strategy produces low error results, there is still a limit beyond which it does not scale. Specifically, as the mapping area grows even wider, the number of local maps increases which in turn causes the amount of required memory to increase. In addition, when it comes to loop closure or in other words the procedure of estimating whether the robot returned to a previously visited point in the map, the required computational power increases linearly or sometimes quadratically with respect to the number of local maps. Consequently, SLAM algorithms suffer from scalability problems, especially when the mapping area becomes too large. Since robots are real-world devices, mapping solutions should be efficient and applicable to the robot's resources, even when these resources are limited. In this thesis we propose a framework which addresses this scalability issue, aiming to reduce the computational needs and memory usage during the SLAM procedure. Additionally, our framework intends to facilitate loop closure, which can become troublesome in large environments. Our framework uses multiple sensors and creates a network of hierarchically structured local maps. In order to assess our framework, we compare it to a technique which produces a network of non-hierarchically structured local maps. Our experiments show that in large areas our framework works ideally; the speedup is encouraging and the RAM memory overhead is negligible or conditionally lower.

Convolutional Neural Network (CNN) inference has gained a significant amount of traction for performing tasks like speech recognition and image classification. To improve the accuracy with which these tasks can be performed, CNNs are typically designed to be deep, encompassing a large number of neural network layers. As a result, the computational intensity and storage requirements increase dramatically, necessitating hardware acceleration to reduce the execution latency. Field-Programmable Gate Arrays (FPGAs) in particular are well-suited for hardware acceleration of CNN inference, since the underlying hardware can be tailored to rapidly and efficiently perform the required operations. To this end, Xilinx introduced the FINN (Fast, Scalable Quantized Neural Network Inference on FPGAs) framework to leverage FPGAs for Neural Network (NN) inference. The FINN end-to-end deep learning framework converts high-level descriptions of CNN models into fast and scalable FPGA inference accelerator designs that are based on a custom dataflow architecture. In this dataflow architecture the input data are streamed in a feed forward fashion through a pipeline of per-layer dedicated compute units, that each have on-chip access to the associated NN parameters. In order to keep the compute units occupied, specific throughput requirements have to be satisfied by the memory subsystem. These throughput requirements directly dictate the shapes of the on-chip buffers that contain the NN parameter values. Especially for accelerators that exploit a high degree of parallelism, these memory shapes map poorly to the available on-chip memory resources of FPGA devices. As a result, these resources are typically underutilized, which leads an On-Chip Memory (OCM) deficiency, and limits the amount of parallelism that can be exploited. In this thesis, a methodology is proposed that improves the mapping efficiency of NN parameter buffers to the embedded Block RAM (BRAM) resources on FPGAs, without negatively impacting the accelerator throughput. To accomplish this, an architecture is proposed where the memory subsystem and compute units are decoupled, and operate as a producer-consumer system. Within this architecture, the memory subsystem functions at a higher clock frequency relative to the compute units, which enables the memory subsystem to match the consumption rate of the compute units when multiple NN parameter buffers are clustered within the same BRAM instance. Furthermore, a genetic algorithm is used to find optimal group arrangements for these clusters such that the mapping efficiency is improved, and the throughput requirements are still met. The proposed methodology has been applied to a number of CNN accelerators, and demonstrates BRAM reductions of up to 30%. The observed BRAM reductions enable existing FINN accelerator designs to be ported to smaller FPGA devices while maintaining the computational throughput.

As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thus prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene’s excellent electronic properties, may serve as basic structures for carbon-based nanoelectronics. However, the graphene intrinsic energy bandgap absence hinders GNR-based devices and circuits implementation. As a result, en route to graphene-based logic circuits, finding a way to open a sizable energy bandgap, externally control GNR’s conduction, and construct reliable high-performance graphene-based gates are the main desideratum. To this end, first, we propose a GNR-based structure (building block) by extending it with additional top gates and back gate while considering five GNR shapes with zigzag edges in order to open a sizeable bandgap, and further investigate GNR geometry and contact topology influence on its conductance and current characteristics. Second, we present a methodology of encoding the desired Boolean logic transfer function into the GNR electrical characteristics, i.e., conduction maps, and then evaluate the effect of VDD variation on GNR conductance. Moreover, we find a proper external electric mean (e.g., top gates and back gates) to control the GNR behavior. Third, we develop a parameterized Verilog-A SPICEcompatible GNR model based on Non-Equilibrium Green’s Function (NEGF)-Landauer formalism that builds upon an accurate physics formalization, which enables to symbiotically exploit accurate physics results from Matlab Simulink and optimized SPICE circuit solvers (e.g., Spectre, HSPICE). Subsequently, we construct graphene-based Boolean gates by means of two complementary GNRs, and design a GNR-based 1-bit Full Adder and a SRAM cell. Finally, we extend the NEGF-Landauer simulation framework with the self-consistent Born approximation while taking into account the temperature-induced phenomena in GNR electron transport, i.e., electron-phonon interactions for both optical and acoustic phonons, and further explore the graphene-based gates performance robustness under temperature variations.@en

The availability of inexpensive and powerful processors provides the means for the computation ecosystem to change its fundamental paradigm towards the Internet of Things (IoT) where ubiquitous nanosystems add intelligence to every object that surrounds us. The new trend for most of those systems is to autonomously operate into a “zero-power” regime, i.e., manage their energy budget in such a way that they can provide the required functionality without any service until they become obsolete. Considering that these systems are most of the time inactive, the static power is the dominant power consumption component, thus the most effective way to fulfill the “zero-power” operation requirement is to diminish the energy consumption into the so called sleep/idle mode. The semiconductor community has been addressing the static power reduction issue at device level, but for the CMOS technology the effectiveness of such approach is limited by the interdependence between static power consumption and device performance. In view of this observation this thesis focuses on improving the energy efficiency of electronic products, battery-powered, and autonomous ones by making use of emerging leakage proof technologies in conjunction with the versatile CMOS counterpart. First, we performed a design space exploration to identify the most promising NEMFET geometries and to evaluate their potential performance in terms of switching delay, current capability, and leakage. Moreover we compared those parameters of interest with the ones offered by traditional transistors utilized in up to date CMOS technologies. Second, we assessed the NEMFET potential when utilized as sleep transistor in circuits featuring 2D cell based power gating, and find out if NEMFETs constitute a viable alternative to High - VTH FETs in sleep mode circuits. Furthermore, we proposed a novel 3D power management approach that attempts to alleviate issues associated with the NEMS utilization as sleep transistor in CMOS power gated integrated circuits. Given the two designs, we evaluated the 2D and 3D NEMFET based power management implementations energy efficiency when embedded into a computation platform executing a bio-medical sensing application. Third, we introduced a NEMFET based logic family tailored to the implementation of ultra-low energy functional units and processors. Fourth, we proposed a memory cell that relies on a NEMFET based inverter designed in such a way that no short circuit current can occur. Finally, we proposed and evaluated the “zero-energy” operation scenario potential of an improved version of the 3D-Stacked NEMS based power management architecture.@en

The human brain is a natural high-performance computing systemwith outstanding properties, e.g., ultra-low energy consumption, highly parallel information processing, suitability for solving complex tasks, and robustness. As such, numerous attempts have been made to devise neuromorphic systems able to achieve brain-akin computation abilities, which can aid in understanding the complex human brain functionality and can be utilized to solve complex problems, e.g., pattern recognition and data mining. However, the fact that human brain comprises billions of neurons, which are the fundamental information processing units, and trillions of synapses that interconnect them makes the design and implementation of large-scale brain-inspired computing systems quite a challenging task. Graphene appears to be a promising candidate for scalable neuromorphic implementations as it exhibits a wealth of outstanding properties, e.g., ballistic transport, ultimate thinness, flexibility, and graphene devices are capable of emulating complex nonlinear functions and can be readily tuned to provide various conduction dynamicswhile preserving low energy operation and small footprint. Moreover, graphene is biocompatible, which offers perspectives for graphene-based neuromorphic bio-interfaces. This thesis aims to investigate graphene’s potential to enable scalable and energy effective neuromorphic computing. To this end, we first introduce an atomistic-level simulation model for calculating graphene electronic transport properties, that captures the hysteresis effects induced by interface charges trapping/detrapping phenomena. Second, we propose a generic graphene based synapse, which can be tailored to emulate different synaptic plasticity types by properly modifying its Graphene NanoRibbon (GNR) shape and contacts topology, as well as applying external voltages. Subsequently, we introduce a compact graphene-based integrate-and-fire spiking neuron that mimics the basic spiking neuronal dynamics. We further propose a basic SpikingNeuralNetwork (SNN) unit,which can be utilized to implement complex graphene-based SNNstructures. Finally,we introduce a reconfigurable graphene-based SNN architecture and a training methodology for obtaining the initial SNN synaptic weight values. We demonstrate the feasibility of the synaptic weights training methodology and the practical capabilities of the proposedSNNarchitecture by applying them to solve character recognition and edge detection problems. Our experiments clearly indicate that the proposed graphene-based neuromorphic approach enables lowenergy operation at small chip real estate footprint, which are enabling factors for the realization of scalable energy-efficient SNN implementations. @en

As advances in silicone CMOS technology steadily plateau, new avenues of electronics design must be explored. Graphene Nanoribbons (GNRs) are a potential solution. Current GNR designs require wasteful exhaustive searches for the required device topologies, limiting the size of the solution space that can be searched. This is fine for simple circuits, but more complex functionality requires a different approach. This work presents a new way of identifying suitable GNR device topologies for any functionality. It also presents an example of this, demonstrating how a circuit using the resultant GNR devices can outperform conventional, more complex circuits. The proposed methodology uses an evolutionary algorithm to efficiently search a large solution space of possible GNR device topologies. This is done while only having to simulate the behavior of a minuscule fraction of the device topologies in this solution space. The GNR devices found by this evolutionary algorithm are used to implement a 4-bit Analog-to-Digital Converter (ADC), where each bit of the circuit consists of only a couple of GNR devices, in contrast to the many more transistors required for conventional designs. The resulting ADC circuit performs better than conventional ADC designs in terms of energy cost, conversion delay, and required circuit area by several orders of magnitude.

Real-time (RT) systems are widespread over different industries, e.g., healthcare, robotics, manufacturing, machine vision, etc. These systems consist of a hardware and software part that execute an RT application. These systems require a bounded and predictable time response on incoming events and execute all input and output (IO) tasks simultaneously. To ensure this concurrent behavior, the different IO devices are synchronized to achieve a common time notion. The implementation of time notion in systems can differ and therefore various types of synchronization exist, e.g. in-band and out-of-band. In-band synchronization utilizes the general communication channel to distribute time information, contrary to out-of-band synchronization which uses an external wire to transfer the time signals. As the in-band type implies the synchronization transactions flow together with the general traffic, the synchronization mechanisms are often implemented in the interconnect protocol. This integration limits the choice for a feasible synchronization protocol as this choice is dependent on that of the interconnect due to restricting communication requirements of RT applications. Current synchronization protocols are often limited to sub-microsecond (μs) latency variations and/or partially rely on an out-of-band principle. The goal of this master thesis is to find a solution that is able to achieve in-band synchronization with nanosecond (ns) range jitter. The proposed design is optimized towards nanosecond-scale jitter, by taking implementation challenges of Precision Time Protocol (PTP) into account, and is separate from the choice of interconnect. PTP is an existing synchronization mechanism which retrieves the differences in time notion (offsets) across multiple devices while accounting for transmission latency to each individual device. The implementation of PTP can result in limited performance in terms of jitter. The design focuses on minimizing this jitter with increasing the accuracy and robustness of the PTP synchronization algorithm by improving the precision of timestamps and filtering the calculated offsets for outliers. The synchronization mechanism was evaluated through simulation and validation in hardware. This master thesis presents a Proof of Concept (PoC) that can be implemented into real-world RT systems. It consists of two devices synchronizing to one reference device using the proposed synchronization mechanism. The PoC achieves down to 7 ns jitter, which was not reached by feasible existing in-band synchronization yet.