CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network
Huiyi Gu (Beihang University)
Xiaotao Jia (Beihang University)
Yuhao Liu (Beihang University)
Jianlei Yang (Beihang University)
Xueyan Wang (Beihang University)
Youguang Zhang (Beihang University)
Sorin Dan Cotofana (TU Delft - Computer Engineering)
Weisheng Zhao (Beihang University)
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Abstract
Bayesian neural network (BNN) has gradually attracted researchers' attention with its uncertainty representation and high robustness. However, high computational complexity, large number of sampling operations, and the von-Neumann architecture make a great limitation for the further deployment of BNN on edge devices. In this article, a new computing-in-MRAM BNN architecture (CiM-BNN) is proposed for stochastic computing (SC)-based BNN to alleviate these problems. In SC domain, neural network parameters are represented in bitstream format. In order to leverage the characteristics of bitstreams, CiM-BNN redesigns the computing-in-memory architecture without complex peripheral circuit requirements and MRAM state flipping. Additionally, real-time Gaussian random number generators are designed using MRAM's stochastic property to further improve energy efficiency. Cadence Virtuoso is used to evaluate the proposed architecture. Simulation results show that energy consumption is reduced more than 93.6% with slight accuracy decrease compared to FPGA implementation with von-Neumann architecture in SC domain.