As advances in silicone CMOS technology steadily plateau, new avenues of electronics design must be explored. Graphene Nanoribbons (GNRs) are a potential solution. Current GNR designs require wasteful exhaustive searches for the required device topologies, limiting the size of the solution space that can be searched. This is fine for simple circuits, but more complex functionality requires a different approach. This work presents a new way of identifying suitable GNR device topologies for any functionality. It also presents an example of this, demonstrating how a circuit using the resultant GNR devices can outperform conventional, more complex circuits.

The proposed methodology uses an evolutionary algorithm to efficiently search a large solution space of possible GNR device topologies. This is done while only having to simulate the behavior of a minuscule fraction of the device topologies in this solution space. The GNR devices found by this evolutionary algorithm are used to implement a 4-bit Analog-to-Digital Converter (ADC), where each bit of the circuit consists of only a couple of GNR devices, in contrast to the many more transistors required for conventional designs.

The resulting ADC circuit performs better than conventional ADC designs in terms of energy cost, conversion delay, and required circuit area by several orders of magnitude.

Real-time (RT) systems are widespread over different industries, e.g., healthcare, robotics, manufacturing, machine vision, etc. These systems consist of a hardware and software part that execute an RT application. These systems require a bounded and predictable time response on incoming events and execute all input and output (IO) tasks simultaneously. To ensure this concurrent behavior, the different IO devices are synchronized to achieve a common time notion. The implementation of time notion in systems can differ and therefore
various types of synchronization exist, e.g. in-band and out-of-band. In-band synchronization utilizes the general communication channel to distribute time information, contrary to out-of-band synchronization which uses an external wire to transfer the time signals. As the in-band type implies the synchronization transactions flow together with the general traffic, the synchronization mechanisms are often implemented in the interconnect protocol. This integration limits the choice for a feasible synchronization protocol as this choice is dependent on that of the interconnect due to restricting communication requirements of RT applications. Current synchronization protocols are often limited to sub-microsecond (μs) latency variations and/or partially rely on an out-of-band principle. The goal of this master thesis is to find a solution that is able to achieve in-band synchronization with nanosecond (ns) range jitter. The proposed design is optimized towards nanosecond-scale jitter, by taking implementation challenges of Precision Time Protocol (PTP) into account, and is separate from the choice of interconnect. PTP is an existing synchronization mechanism which retrieves the differences in time notion (offsets) across multiple devices while accounting for transmission latency to each individual device. The implementation of PTP can result in limited performance in terms of jitter. The design focuses on minimizing this jitter with increasing the accuracy and robustness of the PTP synchronization algorithm by improving the precision of timestamps and filtering the calculated offsets for outliers. The synchronization mechanism was evaluated through simulation and validation in hardware. This master thesis presents a Proof of Concept (PoC) that can be implemented into real-world RT systems. It consists of two devices synchronizing to one reference device using the proposed synchronization mechanism. The PoC achieves down to 7 ns jitter, which was not reached by feasible existing in-band synchronization yet.

FINN is a framework developed by Xilinx Research Labs that compiles Deep Neural Network software descriptions into fast and scalable dataflow architectures for inference acceleration on FPGAs. The dataflow
architectures are network dependent, sized according to the user-defined throughput requirements, and constrained by available resources on the user-specified FPGA board. Synthesising large neural network designs
with a high degree of configurability leads to large build times, spanning from hours to days, to build an entire network. Thus, the first objective of this thesis is to explore and propose a modified FINN accelerator construction methodology that can substantially reduce the build times. The main idea behind our proposal is to reduce the granularity of the architecture to reduce the size of synthesis jobs and to enable logic reuse within and across neural network layers. Using this method, up to 12× speedup in High-Level Synthesis times and up to 2× speedup in end-to-end build times of accelerator networks are achieved.
The second limitation that this work addresses relates to the performance scalability of FINN generated architectures. There are two modes of parallelism in FINN that currently provide performance scaling in convolution operations. The first factor, which modifies the number of Processing Elements (PEs), parallelises along the input channels of a convolutional layer and the second factor, that modifies the number of Single Instruction Multiple Data (SIMD) lanes present in each PE, parallelises along the number of output channels of
the convolution. Computations are currently not parallelisable across the non-depth dimensions of images, i.e., the side containing pixels of images that faces the viewer. This limitation can restrict the achievable performance for networks that contain layers with large image dimensions and shallow depth dimension. The second part of this work leverages the fine-grained construction methodology to augment FINN performance scaling. The proposed approach introduces a generic FINN modification that enables pixel-level parallelism,
i.e., multiple output pixels of a convolutional layer can be processed simultaneously by performing Multiple Matrix Vector (MMV) multiplications at the same time. Using this generic method, MMV number of pixels can be processed simultaneously, an MMV times throughput increase can be obtained at the cost of less than MMV × additional resources.

Recently, it has become popular to use Convolutional Neural Networks (CNNs) in embedded and portable devices. The popularity is based on their high accuracy rate in the field of Computer Vision (CV). However, CNNs are computationally intensive due to the convolutional layer, which accounts for over 90% of the operations. To overcome this problem, many researchers have exerted efforts to develop parallel and customised accelerators. Methods utilised in the accelerators range from bit optimisation to using fixed-point arithmetic, and to reducing the size of the network. Some researchers have also explored alternative computing paradigms such as Stochastic Computing (SC). The great advantage of SC is its ability to perform complex arithmetic with simple hardware. However, a major problem of SC is the trade-off between latency and accuracy. Thus, there have been several attempts to mitigate this factor, ranging from improving the generation of stochastic numbers to parallel bitstreams, to early terminations. This thesis proposes StoHej, a new SC multiplier design that combines stochastic bitstreams and complementary events. The multiplier has two input types, the first is the neural network feature value and the second is the weight value. The weight value determines how many iterations the computation requires. A complement event is utilised if the weight value is greater or equal to $0.5$ since the complement of the event yields a smaller number. Thus, the worst-case latency has been reduced from O(N) to O(N/2). The proposed multiplier was compared with a Conventional Stochastic Computer (CSC) multiplier and the BISC-MVM multiplier, which is the state-of-the-art for SC multipliers that uses an early termination mechanism. All multipliers were first tested in a software simulation in a general context. Accuracy and latency were measured in a software simulation. The results from these simulations showed a 3.2x speedup for the proposed design compared to BISC-MVM, with no increase in computational errors. Then, StoHej and BISC-MVM were tested in a CNN inference application with the MNIST dataset. The multipliers were used in a Multiply-Accumulate (MAC) array that was implemented on an FPGA. The results from the experiment show that StoHej had a 1.7x speedup and no loss in accuracy compared to BISC-MVM. StoHej's energy consumption was reduced by 40% when compared to BISC-MVM. The Area-Delay Product (ADP) of StoHej was 30% smaller than BISC-MVM. StoHej's Area-Delay-Energy Product is 2.3x smaller than the BISC-MVM multiplier.

This thesis evaluates standard statistical and machine learning models for early fault detection for Valve Regulated Lead-Acid (VRLA) batteries in uninterruptible power supply (UPS) units. Unexpected battery failures in emergency support systems throughout CERN can endanger working personnel. Thus the minimization of downtime of such battery systems is essential. Previous research conducted in a Tencent Datacenter using traditional regression models such as Gradient Boosting Decision Tree (GBDT) resulted in a 98% accurate prediction model that can predict 15 days in advance of a battery unit failure. The main features were the pack resistance's standard deviation, relative voltage and relative resistance.
In this study conducted at CERN, the goal was to get a similarly well-performing regression or machine learning model without the possibility to obtain the running average of internal resistance of the battery unit.
Throughout the study, different traditional regression algorithms were considered, but eventually, a predictive model using neural networks was selected. Neural networks provide a more comprehensive and more accurate when it comes to nonlinear fitting. The most fitting model for the given dataset was an Recurrent Neural Network (RNN) model with Adagrad compiler optimizer using Rectified Linear Unit (RELU), in combination with a sigmoid, activation function. However, even with the optimal neural network configuration, the model's overall accuracy does not perform sufficiently to conclude an overall positive result. The lack of internal resistance metric appears to be so significant that the precision of the model has lacked evidence of correctness. Thus, to get significant predictability of a VRLA battery, it is essential to measure the impedance of the battery units.

As CMOS scaling approaches the atomic feature size limit which results in a high power density and current leakage, low reliability and increased time and production cost, the need for new materials and devices is increasing. One of the promising materials to replace silicon based devices is graphene nano-ribbons (GNRs) due to its remarkable electronic properties. Theoretical models suggest that 30nm GNR structures can mimic the behaviour of basic Boolean logic gates such as inverter, buffer, or and nor gates while reducing 30x times the propagation delay and using 3000x less gate active area compared to the equivalent CMOS realization. The main goal of this thesis is to fabricate GNR devices that can be ultimately used as building blocks for Boolean logic gates, analyse the limitations of achieving sub-50nm patterns and study the edge termination of the formed GNR patterns. GNR patterns are explored using a simulation model, which can be used for complementary Boolean logic gates. The designed graphene patterns are simulated using tight binding model to calculate the electronic band structure and construct a Hamiltonian matrix. This is followed by calculation of the electronic states and Fermi energies. Non equilibrium Green function (NEGF) models the electrons and holes distribution trough the GNR pattern and the rate at which the charge carriers are transmitted from the source to the drain when they propagate through the device. The result from the NEGF function is used to calculate the charge density using 3D POISSON from which the current through the graphene surface is determined. Finally, with known gate voltages and current, the conductance is found for four different structures in 10 nm and 30 nm technology. By changing the way the structures are connected as pull-up and pull-down network, the behaviour of inverter, buffer, or, and nor gates are obtained. The patterns from the simulation model with 30 nm feature size are used to create a design for devices to be fabricated. In addition, the design includes devices with minimal dimensions from 50 nm to 200 nm, squares, hexagons and pentagons with different dimensions starting from 1 um up to 10 um. For this project, graphene grown by chemical vapour deposition (CVD) was transferred to silicon dioxide samples on which the design of the structures is fabricated. The fabrication process consist of five steps. First, the samples are spin coated with polymethyl-methacrylate (PMMA). Second, electron beam lithography (EBL) is used to pattern the structures, by exposing parts of the resist. Next, the exposed areas are developed in order to remove the resist with introduced damage from the exposure. This is followed by etching the exposed parts of the graphene using oxygen plasma or hydrogen plasma. Finally, the remaining resist is cleaned with acetone. Characterisation of the patterns is performed using Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM). From the Raman measurements it was found that the edge termination is most likely random and defects are introduced to the lattice of the graphene patterns with left contaminants from the polymer. The achieved minimal feature size of the devices is 50 nm, which was confirmed using AFM and SEM. In addition to the morphological characterisation of the samples, electrical measurements are performed and from the transport characteristics, the electron and hole mobilities of mono layer graphene are derived.

Convolutional Neural Network (CNN) inference has gained a significant amount of traction for performing tasks like speech recognition and image classification. To improve the accuracy with which these tasks can be performed, CNNs are typically designed to be deep, encompassing a large number of neural network layers. As a result, the computational intensity and storage requirements increase dramatically, necessitating hardware acceleration to reduce the execution latency. Field-Programmable Gate Arrays (FPGAs) in particular are well-suited for hardware acceleration of CNN inference, since the underlying hardware can be tailored to rapidly and efficiently perform the required operations. To this end, Xilinx introduced the FINN (Fast, Scalable Quantized Neural Network Inference on FPGAs) framework to leverage FPGAs for Neural Network (NN) inference. The FINN end-to-end deep learning framework converts high-level descriptions of CNN models into fast and scalable FPGA inference accelerator designs that are based on a custom dataflow architecture. In this dataflow architecture the input data are streamed in a feed forward fashion through a pipeline of per-layer dedicated compute units, that each have on-chip access to the associated NN parameters. In order to keep the compute units occupied, specific throughput requirements have to be satisfied by the memory subsystem. These throughput requirements directly dictate the shapes of the on-chip buffers that contain the NN parameter values. Especially for accelerators that exploit a high degree of parallelism, these memory shapes map poorly to the available on-chip memory resources of FPGA devices. As a result, these resources are typically underutilized, which leads an On-Chip Memory (OCM) deficiency, and limits the amount of parallelism that can be exploited. In this thesis, a methodology is proposed that improves the mapping efficiency of NN parameter buffers to the embedded Block RAM (BRAM) resources on FPGAs, without negatively impacting the accelerator throughput. To accomplish this, an architecture is proposed where the memory subsystem and compute units are decoupled, and operate as a producer-consumer system. Within this architecture, the memory subsystem functions at a higher clock frequency relative to the compute units, which enables the memory subsystem to match the consumption rate of the compute units when multiple NN parameter buffers are clustered within the same BRAM instance. Furthermore, a genetic algorithm is used to find optimal group arrangements for these clusters such that the mapping efficiency is improved, and the throughput requirements are still met. The proposed methodology has been applied to a number of CNN accelerators, and demonstrates BRAM reductions of up to 30%. The observed BRAM reductions enable existing FINN accelerator designs to be ported to smaller FPGA devices while maintaining the computational throughput.

As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thus prompting for research on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene’s excellent electronic properties, may serve as basic structures for carbon-based nanoelectronics. However, the graphene intrinsic energy bandgap absence hinders GNR-based devices and circuits implementation. As a result, en route to graphene-based logic circuits, finding a way to open a sizable energy bandgap, externally control GNR’s conduction, and construct reliable high-performance graphene-based gates are the main desideratum. To this end, first, we propose a GNR-based structure (building block) by extending it with additional top gates and back gate while considering five GNR shapes with zigzag edges in order to open a sizeable bandgap, and further investigate GNR geometry and contact topology influence on its conductance and current characteristics. Second, we present a methodology of encoding the desired Boolean logic transfer function into the GNR electrical characteristics, i.e., conduction maps, and then evaluate the effect of VDD variation on GNR conductance. Moreover, we find a proper external electric mean (e.g., top gates and back gates) to control the GNR behavior. Third, we develop a parameterized Verilog-A SPICEcompatible GNR model based on Non-Equilibrium Green’s Function (NEGF)-Landauer formalism that builds upon an accurate physics formalization, which enables to symbiotically exploit accurate physics results from Matlab Simulink and optimized SPICE circuit solvers (e.g., Spectre, HSPICE). Subsequently, we construct graphene-based Boolean gates by means of two complementary GNRs, and design a GNR-based 1-bit Full Adder and a SRAM cell. Finally, we extend the NEGF-Landauer simulation framework with the self-consistent Born approximation while taking into account the temperature-induced phenomena in GNR electron transport, i.e., electron-phonon interactions for both optical and acoustic phonons, and further explore the graphene-based gates performance robustness under temperature variations.

At the core of state of the art microelectronic industry's drive for better technology, lies the continuing advancement in the development of Integrated Circuits using highly complex lithography machines, known as lithosteppers, which embed complex mechanical sub-systems performing intricate motions.
These systems are controlled by means of custom real-time computing platforms containing off-the-shelf and specialized hardware components, and are optimized to keep pace with the continuing growing trend in performance requirements.
At the ASML Twinscan lithostepper's heart resides the Control Architecture Reference Model (CARM) motion control platform which manages, among others, the wafer-stage, a multiple degree of freedom module, able to position a 15 kg heavy wafer-table with nanometer accuracy at extremely high acceleration and velocity.
As the industry requirements for feature-size, overlay accuracy, and throughput keep increasing, the ASML lithosteppers, and the CARM platform in particular, should anticipate these demands by making early changes and upgrades with respect to computational performance and accuracy.
Given that the current lithostepper configurations are not capable of sustaining the anticipated updates, which requires the increase of the control loop execution frequency from 20kHz to 40kHz, an early evaluation of potential CARM High Performance Process Controller (HPPC) successors has been performed. This indicated that the NXP-Freescale T4240 processor can potentially fulfill the expected requirements, however, the evaluation lacks accuracy as it was performed on a benchmark code not reflecting the actual CARM workload. To circumvent this problem, in this thesis, we introduce a more accurate evaluation methodology, which relies on the actual motion control application running on the HPPC and is able to capture aspects as scheduling, parallelism, and processor resource usage.
To this end we develop a set of custom performance benchmarks able to emulate the CARM environment and evaluate the Freescale T4240 processor in this new context. Our results indicate that the T4240 is able to deliver enough computation power to fulfill the control loop execution frequency upscaling requirement from 20kHz to 40kHz.
Additionally, we demonstrate that due to its clustered hardware architecture one T4240 can sustain 20kHz loop execution frequency for the workload of three current HPPCs, which suggest that its utilization in current lithosteppers can be beneficial.

Mechatronic embedded control systems are becoming increasingly sophisticated and computationally demanding. These systems typically consists of multiple controllers, which coordinate the actuators and apply feedback based on data collected by sensors. Often the underlying control strategy is entirely described in a software application, which allows for hardware independence and adds the ability to conveniently change algorithms. In order to increase application throughput, a commonly used approach is to divide the application into smaller units called tasks and execute them in parallel using multi-core hardware. In this thesis an automated multi-core aware scheduling and assignation approach is designed for an industrial-sized mechatronic control software platform, more specific the Prodrive Motion Platform (PMP). PMP can be applied in a wide range of products, e.g. wafer scanners, robots, elevators. A key feature of PMP is flexibility, which allows it to be utilized in combination with a wide variety of both controllable hardware (actuators, sensors) as well as computational hardware. As a direct consequence, PMP supports many different customers and corresponding requirements. Within PMP, a customer typically defines the application, which is then translated into a set of tasks. This task-set is then scheduled and assigned onto the available multi-core hardware resources. In order to meet timing-constraints, the current scheduling approach relies on a time-consuming manual process, which provides a limited amount of tuning options, and neither considers task workloads, nor inter-core communication costs. Given these short-comings, this solution proved to be unsuited for upcoming PMP products. To address the aforementioned issues, we first review state of the art scheduling solutions and introduce an extensible task measurement framework. Subsequently, we evaluate various scheduling approaches on current PMP applications and identify two algorithms, namely, Internalization using Load Balancing and DCS, that are able to automatically find schedules, whilst still meeting application timing-constraints. Besides enabling to schedule new applications within upcoming PMP products, performance improvements of ~3.3% and ~2.0% were observed by Internalization using Load Balancing and DCS, respectively, compared to the original scheduling approach within the multi-core PMP product PPCx3. Last but not least it is shown that within a relatively new product XEONx3, our approach provides performance improvements of 34.30% up to 49.61%, depending on the utilized scheduling algorithm.

Within the past half century, Integrated Circuits (ICs) experienced an aggressive, performance driven, technology feature size scaling. As the technology scaled into the deep nanometer range, physical and quantum mechanical effects that were previously irrelevant become influential, or even dominant, resulting in, e.g., not any longer negligible leakage currents. When attempting to pattern such small-geometry dimensions, the variability of technological parameters considerably gained importance. Furthermore, it became more difficult to reliably handle and integrate such a huge number of tiny transistors into large scale ICs, considering also that a substantial increase in power density needed to be taken into account. Scaling induced performance was no longer sufficient for delivering the expected improvements, which lead to a paradigm switch from uniprocessors to multiprocessor micro-architectures. At the same time, since for certain application domains, such as big data and Internet of things, the to be processed data amount increases substantially, computing system designers become more concerned with ensuring data availability than with reducing functional units latency. As a result, state of the art computing systems employ complex memory hierarchies, consisting of up to four cache levels with multiple shared scenarios, making memory a dominant design element that considerably influences the overall system performance and correct behavior. In this context, 3D Stacked Integrated Circuit (3D SIC) technology emerges as a promising avenue in enabling new design opportunities since it provides the means to interconnect devices with short vertical wires. In this thesis we address the above mentioned memory challenges by investigating the 3D SIC technology utilization in memory designs, as follows. First, we propose a novel banked multi-port polyhedral memory that provides an enriched access mechanism set with a very low bank conflict rate and we evaluate its potential in shared caches. Second, we propose a low power hybrid memory in which 3D technology allows for the smooth co-integration of: (i) short circuit current free Nano-Electro-Mechanical Field Effect Transistor (NEMFET) based inverters for data storage, and, (ii) CMOS-based logic for read/write operations and data preservation. Third, we propose a memory repair framework that exploits the 3D vertical proximity for inter-die redundant resources sharing. Finally, we propose novel schemes for performing user transparent multi-error correction and detection, with the same or even lower redundancy than the one required by state of the art extended Hamming single error correction schemes.

The project focuses on the hardware-software co design of a LoRaWAN based industrial IoT gateway used for proprietary applications. Long Range Wide Area Network, abbreviated as LoRaWAN is a network and data layer running over the LoRa PHY layer which operates at 868 MHz[29]. The surge in LoRa has led big market players like SemTech to licence devices operating over a free network. Also gateway manufacturers have seized on the opportunity of this growing market and 2 industrial gateways, [15], [27] have captured most of the market. In order to break this monopoly, FactoryLab B.V, an Industrial IoT company from Zwijndrecht, The Netherlands has developed a low cost Linux based gateway which can be used for proprietary applications. The project aims at developing and comparing the gateway with industry standards. Although the hardware for the gateway couldn’t be tested in time for the finalization of this report, various tests are performed using an improvised hardware setup which emulates the FactoryLab hardware and the results approximated and compared to the industrial gateways. The Range to Cost ratio for the test setup was calculated to be 4.8 meters/euro and when pitched against the other gateways, showed a maximum increase of 26.6%.