In this paper we introduce a frequency-domain pulse detection method that is suitable for in-situ implementation at detector-level, for low-power, self-triggered air shower detectors. We propose a graphene-based architecture, and demonstrate its correct operation by means of SPICE simulations. The utilized graphene-based devices operate at low supply voltage, consume low energy per spike, and exhibit small footprints, which are essential properties for large-scale, energy-efficient implementations. The proposed method is particularly effective for very low (Signal-to-Noise Ratio) SNR scenarios, and is broadband noise resilient up to a certain extent, and (Radio Frequency) RF narrowband noise agnostic. Comparison results against time-domain signal-over-threshold trigger indicates that the proposed method can outperform its counterpart in terms of trigger efficiency by up to 26× and 47×, when using 1 and 2 frequency components, respectively, especially for very low SNR scenarios (up to -42 dB) where time-domain methods are largely impaired. Furthermore, the proposed method does not require RF filtering in advance, and can coexist with other noise pulses. Thus, high detection efficiency that goes in tandem with high purity (low number of false positives) becomes tenable with proposed approach.

In recent years, Spin Waves (SWs) have emerged as a promising CMOS alternative technology, and SW interference-based majority gates have been proposed and experimentally realized. In this paper, we pursue a different computation avenue and introduce a SW device able to evaluate 2×2 2D convolution, which is a fundamental element for the implementation of Convolutional Neural Networks (CNNs). Assuming that the window pixels are P = [p₁, p₂; p₃, p₄] and the kernel is K = [k₁, k₂; k₃, k₄] we introduce a device which evaluates the convolution result Σ_{i = 1}⁴ p_i k_i within the SW domain by leveraging SWs inherent mechanisms, i.e., information encoding in SW amplitude and phase, SW amplitude decay due to Gilbert damping, SW interference. After introducing the SW device structure we demonstrate its proper behaviour by means of micromagnetic simulations. We also present power consumption, area, and delay estimates and argue that due to the fact that our proposal does not rely on standard adders and multipliers, it can substantially outperform traditional CMOS-based convolution implementations.

Graphene is well-suited for ultra-low-power (ULP) nano-electronics due to its exceptional characteristics like ballistic transport and its ability to engineer structures fea-turing a geometry-induced bandgap. Identifying the conditions necessary for achieving the maximum level of performance and of power-efficiency frequently requires a design space exploration (DSE). By means of calibration and external regulation of the supply voltage, the ULP graphene-nanoribbon (GNR) ring oscillator presented in this paper is capable of exceeding the performance of its 7 nm FinFET counterpart both in terms of maximum frequency and of power-efficiency. Under nominal supply voltage conditions we achieve a 1.89× higher output frequency while simultaneously reducing the power consumption by 553.8× and achieving a 812× higher power efficiency. After performing a DSE and lever-aging both externally-applied supply voltage modulation and output frequency calibration we achieved a 4.81× higher maximum output frequency operation mode and a 242× higher maximum power-efficiency operation mode when configuring both blocks for peak performance for each mode.

It is envisaged that spintronic logic devices will ultimately be utilized in hybrid CMOS-spintronic systems where signal interconversion between magnetic and electrical domains via transducers takes place. This underscores the vital role of transducers in influencing the overall performance of such hybrid systems. This paper addresses the question: Can spintronic circuits based on Magnetic Tunnel Junction (MTJ) transducers outperform their state-of-the-art CMOS counterparts? To this end, we use the EPFL (École Polytechnique Fédérale de Lausanne) combinational benchmark sets, synthesize them in 7 nm CMOS and in MTJ transducer based spintronic technologies, and compare the two implementation methods in terms of Energy-Delay-Product (EDP). To fully utilize the technologies' potential, CMOS and spintronic implementations are built upon standard Boolean and Majority Gates, respectively. For the spintronic circuits, we assumed that domain conversion (electric/magnetic to magnetic/electric) is performed by means of MTJs and the computation is accomplished by domain wall (DW)-based majority gates, and considered two EDP estimation scenarios: (i) Uniform Benchmarking, which ignores the circuit's internal structure and only includes domain transducers' power and delay contributions into the calculations, and (ii) Majority-Inverter-Graph Benchmarking, which also embeds the circuit structure, the associated critical path delay and energy consumption by DW propagation. Our results indicate that, for the uniform case, the spintronic route is better suited for the implementation of complex circuits with few inputs and outputs. On the other hand, when the circuit structure is also considered via majority and inverter synthesis, our analysis clearly indicates that in order to match and eventually outperform CMOS performance, MTJ transducers' efficiency has to be improved by 3-4 orders of magnitude. While it is clear that for the time being the MTJ-based-spintronic way cannot compete with CMOS, further technological transducer developments may tip the balance, which, when combined with information non-volatility, may make spintronic implementation for certain applications that require a large number of calculations and have a rather limited amount of interaction with the environment.

This paper introduces a novel approach towards Analog-to-Digital Converter (ADC) implementation that combines Graphene Nanoribbon (GNR) devices capabilities to provide augmented (more complex than a switch) functionality with the fact that each output bit b_i, i∈[0, n-1] of an n-bit ADC is defined as a periodic symmetric function F_i(V_in) with period V_max/2ⁱ, of the ADC input V_in∈[0, V_max]. As such, by making use of the Boolean function implementation methodology with two complementary GNRs, the imple-mentation of an n-bit ADC requires 2n GNR devices. To demonstrate our approach we present the implementation of a 4-bit ADC and the evolutionary algorithm that identifies the GNR topologies required for F_i(V_in), i∈[0,3] evaluation when V_in∈[0,200mV]. We demonstrate the correct functionality of our proposal by means of SPICE simulations and compare it with state-of-the-art counterparts. The comparison indicates that our approach exhibits around five orders of magnitude lower power consumption, is operating at four orders of magnitude larger sample frequency, requires nine orders of magnitude lower real estate, and, in terms of Walden's figures of merit, scores three orders of magnitude better in time per conversion step and nine in energy per conversion step. The required GNR device topologies are identified by means of an evolutionary algorithm, allowing a design space of many trillions of possible devices to be searched by evaluating the behaviour of only a few hundred thousand different topologies.

While Spin Waves (SW) interaction provides natural support for low power Majority (MAJ) gate implementations many hurdles still exists on the road towards the realization of practically relevant SW circuits. In this paper we leave the SW interaction avenue and propose Threshold Logic (TL) inspired SW computing, which relies on successive phase rotations applied to one single SW instead of on the interference of an odd number of SWs. After providing a short TL inside we introduce the SW TL gate concept and discuss the way to mirror TL gate weight and threshold values into physical phase-shifter parameters. Subsequently, we design and demonstrate proper operation of a SW TL based Full Adder (FA) by means of micro-magnetic simulations. We conclude the paper by providing inside on the potential advantages of our proposal by means of a conceptual comparison of MAJ and TL based FA implementations.

Identifying methods to further push the boundaries of existing low-power designs has gained new traction, driven by the wide-scale use of large language models. Graphene is well-suited for ultra-low-power nano-electronics due to its exceptional characteristics like ballistic transport, flexibility, and bio-compatibility. In this paper we investigate the feasibility of using ultra-low-voltage GNR structures, in conjunction with power reduction techniques to implement a GNR-based current-starved ring oscillator. By exploiting their low operating voltage and attofarad range intrinsic capacitances we achieve a 1.89 x higher output frequency while simultaneously reducing the power consumption by 553.8 x and achieving a 812 x higher power efficiency.

Bayesian neural network (BNN) has gradually attracted researchers' attention with its uncertainty representation and high robustness. However, high computational complexity, large number of sampling operations, and the von-Neumann architecture make a great limitation for the further deployment of BNN on edge devices. In this article, a new computing-in-MRAM BNN architecture (CiM-BNN) is proposed for stochastic computing (SC)-based BNN to alleviate these problems. In SC domain, neural network parameters are represented in bitstream format. In order to leverage the characteristics of bitstreams, CiM-BNN redesigns the computing-in-memory architecture without complex peripheral circuit requirements and MRAM state flipping. Additionally, real-time Gaussian random number generators are designed using MRAM's stochastic property to further improve energy efficiency. Cadence Virtuoso is used to evaluate the proposed architecture. Simulation results show that energy consumption is reduced more than 93.6% with slight accuracy decrease compared to FPGA implementation with von-Neumann architecture in SC domain.

Recent theoretical and experimental spintronics developments clearly indicate that Spin Waves (SW) interference based Majority gates (MAJ3) open an alternative road towards ultra low-power circuit implementations potentially capable to outperform CMOS counterparts. However, hurdles still exist, e.g., gate cascading, as due to the very nature of SW interference MAJ3 gates are not input output coherent, i.e., produce output waves with different amplitudes corresponding to ‘weak’ and ‘strong’ majority, which precludes their direct cascading within the SW domain. State of the art designs address this issue by means of hybrid SW-CMOS systems that make use on domain converters, which are energy expensive and diminish if not nullify the ultra-low power promise of the SW-based computing paradigm. In this paper we propose a gate cascading technique that rely on the natural SW amplitude decay while propagating through a magnetic conduit. We demonstrate the concept by constructing the building block MAJ3(MAJ3(In1,In2,In3),In4,In5) and verifying its correct behaviour by means of micromagnetic simulations. We evaluate the proposed design in terms of energy consumption, delay, and area, and our calculations indicate that, when compared with its domain conversion counterpart, our proposal consumes 49.5% less energy, at the expense of 48% area and 76.5% delay overhead, respectively.

In this paper we propose a generic graphene-based Spiking Neural Network (SNN) architecture for pattern recognition and the associated weight values initialization methodology. The SNN has a Winner-Takes-All 3-layer structure and exhibits tuneable recognition accuracy by exploiting interpatterns similarity/dissimilarity. To demonstrate the capabilities of our proposal we present an SNN instance tailored for low resolution MNIST handwritten digits recognition and evaluate its recognition accuracy by means of SPICE simulations. 2 voltage levels are initially utilized for synaptic weight values representation and the recognition accuracy varies from 75.8% to 99.2%, which, together with its compactness and energy efficient (pJ range/spike), suggests that our approach has great potential for edge device implementations.

In the ‘Beyond Moore’s Law’ era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore’s Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries.

The instrumentation amplifier, which incorporates Dynamic Element Matching (DEM) and a resistive network, utilizes a digital controller to reduce gain error by means of averaging. This paper assesses the feasibility of combining, within a general-purpose microcontroller, the appealing DEM, i.e., very accurate resistive ratios ranging between 1 and 15, with the associated versatile and scalable interrupt-aware digital controller. Given a mixedsignal system, a hybrid evaluation environment has been developed to perform relevant testbenches for assessing the systems performance, i.e., DEM controller, muxes, OpAmps, with respect to relevant metrics for integrated digital and mixed-signal circuits, i.e., energy, delay, footprint, precision. When implementing our design in a commercial 180nm technology, the gain precision of a typical amplifier is improved by more than 1800 times, with the error converging to as low as 10s of ppm, for Gaussian mismatch distribution between-1% and 1% with the cost of DEM digital circuitry which adds about 30000 µm² of chip area and will consume 194 µA.

Current Spin Wave (SW) state-of-the-art computing relies on wave interference for achieving low power circuits. Despite recent progress, many hurdles, e.g., gate cascading, fan-out achievement, still exist. In a previous work, we introduced a novel SW phase shift based computation paradigm and demonstrated that an n-input Threshold Logic Gate (TLG) can be implemented with n + 1 phase shifters operating on the same SW. In this paper we further develop this concept by introducing a phase shift amount reading method by means of parametric amplification. We make use of 3-input Majority Gate (MAJ3) as discussion vehicle and introduce a novel majority function evaluation approach which postpone the threshold related calculations to the gate output readout stage. Subsequently, we verify this principle by means of micromagnetic simulations and discus the results. Finally, we utilize the proposed MAJ3 gate to implement a collection of representative logic circuits from the EPFL Combinational Benchmarking Suite and evaluate and compare their area, energy consumption, and Energy Area Product (EAP) with the ones of 7 nm CMOS technology node based counterpart imple-mentations. Our estimations indicate that EAP_CMOS/EAP_SW average value is 5.25 and 2.2 for a SW transducer feature size of 20 nm and 30 nm, respectively.

The robustness of Bayesian neural networks (BNNs) to real-world uncertainties and incompleteness has led to their application in some safety-critical fields. However, evaluating uncertainty during BNN inference requires repeated sampling and feed-forward computing, making them challenging to deploy in low-power or embedded devices. This article proposes the use of stochastic computing (SC) to optimize the hardware performance of BNN inference in terms of energy consumption and hardware utilization. The proposed approach adopts bitstream to represent Gaussian random number and applies it in the inference phase. This allows for the omission of complex transformation computations in the central limit theorem-based Gaussian random number generating (CLT-based GRNG) method and the simplification of multipliers as and operations. Furthermore, an asynchronous parallel pipeline calculation technique is proposed in computing block to enhance operation speed. Compared with conventional binary radix-based BNN, SC-based BNN (StocBNN) realized by FPGA with 128-bit bitstream consumes much less energy consumption and hardware resources with less than 0.1% accuracy decrease when dealing with MNIST/Fashion-MNIST datasets.

In the context of an artificial intelligence and machine learning landscape that is evolving at an unprecedented pace, we propose a low power, high-speed, mixed-signal graphene nanoribbon-based (GNR) McCulloch-Pitts neuron (MCPN) implementation featuring programmable synaptic weights and inhibitory inputs. By definition, a generic MCPN is comprised of two parts, a weighted summation element and a decision element, called a soma. Our summation element implementation uses three distinct non-rectangular GNR devices, biased under specific conditions, to fulfill the roles of current source, low-side and high-side switches. The programmable excitatory and inhibitory synapses were obtained leveraging GNR SRAM cells and logic gates, hence providing the flexibility needed by real-world applications. The decision element's threshold activation function was implemented using a chain of GNR inverter structures which manifest the function's characteristic in the analog domain. Modulation of the decision element's threshold is achieved indirectly by means of a configurable resistive load which is varied depending on the configuration stored in SRAM. Our benchmark results, obtained using a generic 5 by 5 pixel pattern recognition application, reveal that the GNR-based implementation achieves 3.5× less power consumption, 20 × higher speed, while occupying 3 × less active area when compared to its FinFET analog circuit counterpart.

As CMOS feature size vertiginously approaches atomic limits, high leakage and power density and exacer-bating IC production costs are prompting for development of new materials, devices, beyond von-Neumann architectures and computing paradigms. Within this context, graphene has emerged as a promising post-Si front runner, owing to its remarkable properties. In this paper, we propose a generic graphene-based complementary-style Boolean gate structure with memory-lock, that allows logic and non-volatile memory co-location. The gate with memory-lock is composed of 2 cells - a pull-up cell performing the gate Boolean function and a pull-down cell performing the inverted Boolean function. Each cell in turn, has a graphene logic layer that carries out Boolean gates computation, and a graphene memory layer for storing the logic state of the gate. As simulation vehicle we considered an inverter gate with memory-lock. Simulation results indicate a current ratio of write/read to/from memory of 1.64.10²for gate input low, and of 2.55. 10²for gate input high. Furthermore, the inverter with memory-lock exhibits a 128× smaller area footprint when compared to the traditional physically separate logic (e.g., 7nm inverter gate) and memory (e.g., 7nm 6T SRAM cell), establishing the potential of proposed structure with memory-lock for more compact and energy efficient future beyond CMOS nano-electronic implementations, and making it highly promising for high-density computations.

Quantum-dot Cellular Automata (QCA) provide very high scale integration potential, very high switching frequency, and have extremely low power demands, which make the QCA technology quite attractive for the design and implementation of large-scale, high-performance nanoelectronic circuits. However, state-of-the-art QCA circuit designs were not derived by following a set of universal design rules, as is the case of CMOS circuits, and, as a result, it is either impossible or very difficult to combine QCA circuit blocks in effective large-scale circuits. In this paper, we introduce a novel automated design methodology, which builds upon a QCA specific universal design rules set. The proposed methodology assumes the availability of a generic QCA crossbar architecture and provides the means to customize it in order to implement any given logic function. The programming principles and the flow of the proposed automated design tool for crossbar QCA circuits are described analytically and we apply the proposed automated design method for the design of both combinatorial and sequential circuits. The obtained designs demonstrate that the proposed method is functional, easy to use, and provides the desired QCA circuit design unification.

Spin Waves (SWs), by their nature, are excited by means of voltage driven or current driven cells under two modes: Continuous Mode Operation (CMO), and Pulse Mode Operation (PMO). Moreover, the low throughput of the SW technology (caused by its high latency) can be enhanced by wavepipelining which is supported inherently by the SW under the two modes. Therefore, we propose wavepipelined SW based two cascaded Majority gates (SWMGs) circuit and validate it by means of micromagnetic simulations working under CMO and PMO. Our evaluation results indicate that PMO SWMGs circuit consumes 6.7x less energy than CMO SWMGs circuit. In addition, the evaluation shows that the wavepipelined PMO and CMO SWMGs circuit have the same throughput, while they are better than the non-wavepipelined circuit by 2x.

While magnetic solid-state memory has found commercial applications to date, magnetic logic has rather remained on a conceptual level so far. Here, we discuss open challenges of different spintronic logic approaches, which use magnetic excitations for computation. While different logic gate designs have been proposed and proof of concept experiments have been reported, no nontrivial operational spintronic circuit has been demonstrated due to many open challenges in spintronic circuit and system design. Furthermore, the integration of spintronic circuits in CMOS systems will require the usage of transducers between the electric (CMOS) and magnetic domains. We show that these transducers can limit the performance as well as the energy consumption of hybrid CMOS-spintronic systems. Hence, the optimization of transducer efficiency will be a major step towards competitive spintronic logic system.

In this article, we propose an energy-efficient spin wave (SW)-based approximate 4:2 compressor including three- and five-input majority gates. We validate our proposal by means of micromagnetic simulations and assess and compare its performance with state-of-the-art SW 45-nm CMOS and spin-CMOS counterparts. The evaluation results indicate that the proposed compressor consumes 31.5% less energy than its accurate SW-design version. Furthermore, it has the same energy consumption and error rate as a directional coupler (DC)-based approximate compressor, but it exhibits a 3× shorter delay. In addition, it consumes 14% less energy while having a 17% lower average error rate than its approximate 45-nm CMOS counterpart. When compared with other emerging technologies, the proposed compressor outperforms the approximate spin-CMOS-based compressor by three orders of magnitude in terms of energy consumption while providing the same error rate. Finally, the proposed compressor requires the smallest chip real estate measured in terms of devices.