This paper introduces a novel approach towards Analog-to-Digital Converter (ADC) implementation that combines Graphene Nanoribbon (GNR) devices capabilities to provide augmented (more complex than a switch) functionality with the fact that each output bit b_i, i∈[0, n-1] of an n-bit ADC is defined as a periodic symmetric function F_i(V_in) with period V_max/2ⁱ, of the ADC input V_in∈[0, V_max]. As such, by making use of the Boolean function implementation methodology with two complementary GNRs, the imple-mentation of an n-bit ADC requires 2n GNR devices. To demonstrate our approach we present the implementation of a 4-bit ADC and the evolutionary algorithm that identifies the GNR topologies required for F_i(V_in), i∈[0,3] evaluation when V_in∈[0,200mV]. We demonstrate the correct functionality of our proposal by means of SPICE simulations and compare it with state-of-the-art counterparts. The comparison indicates that our approach exhibits around five orders of magnitude lower power consumption, is operating at four orders of magnitude larger sample frequency, requires nine orders of magnitude lower real estate, and, in terms of Walden's figures of merit, scores three orders of magnitude better in time per conversion step and nine in energy per conversion step. The required GNR device topologies are identified by means of an evolutionary algorithm, allowing a design space of many trillions of possible devices to be searched by evaluating the behaviour of only a few hundred thousand different topologies.