Graphene is well-suited for ultra-low-power (ULP) nano-electronics due to its exceptional characteristics like ballistic transport and its ability to engineer structures fea-turing a geometry-induced bandgap. Identifying the conditions necessary for achieving the maximum level of performance and of power-efficiency frequently requires a design space exploration (DSE). By means of calibration and external regulation of the supply voltage, the ULP graphene-nanoribbon (GNR) ring oscillator presented in this paper is capable of exceeding the performance of its 7 nm FinFET counterpart both in terms of maximum frequency and of power-efficiency. Under nominal supply voltage conditions we achieve a 1.89× higher output frequency while simultaneously reducing the power consumption by 553.8× and achieving a 812× higher power efficiency. After performing a DSE and lever-aging both externally-applied supply voltage modulation and output frequency calibration we achieved a 4.81× higher maximum output frequency operation mode and a 242× higher maximum power-efficiency operation mode when configuring both blocks for peak performance for each mode.

The Dynamic Element Matching (DEM) technique’s role is to mitigate mismatch issues in complex, matrix-based systems. Previous work employing a matrix-based random DEM scheme demonstrated enhanced linearity and spectral characteristics in the Digital to Analog Converter’s (DAC) thermometric decoded section. This paper presents the design of an area-optimized, DEM-assisted 9-bit segmented DAC. The optimal segmentation level for area-performance is initially established. Subsequently, to mitigate area constraints from the integral nonlinearity (INL) requirement and improve spectral performance, we utilize the matrix-based DEM engine from prior research. The proposed 9-bit DAC, implemented in a commercial 180 nm CMOS process, achieves a total harmonic distortion (THD) of-79 dB and a spurious-free dynamic range (SFDR) of 79 dB, resulting in 8× and 16× improvements in SFDR and THD, respectively, over its non-DEM counterpart.

In this work we present the pulsed current (PC) electrodeposition of Sn-Cu-Ni alloy as lead-free solder candidate, from choline chloride – ethylene glycol eutectic mixtures (1:2 molar ratio) onto copper metallic substrates. Electrolytes containing Sn²⁺, Cu²⁺ and Ni²⁺ salts in the selected deep eutectic solvent have been considered. The effect of the applied frequency of PC on the morphology, composition and melting point of the alloy is discussed and compared to the ones obtained using direct current (DC) plating mode. A refinement of the grain size and lower melting temperature of the alloy were noticed when pulsed current was applied. A comparative analysis of the electrochemical corrosion behaviour at macro- and micro- scale has been performed in 0.5 M and 0.1 M NaCl solutions involving potentiodynamic polarization curves, electrochemical impedance spectroscopy (EIS) and scanning vibrating electrode (SVET) techniques. Furthermore, an analysis after 96 h of exposure to salt mist test simulating a corrosive attack in harsh environment is presented, too. The obtained results showed enhanced corrosion resistance of the ternary alloys electrodeposited under PC conditions (the best for 1.67 Hz frequency) as compared to those using DC. Additionally, Raman spectroscopy evidenced the presence of tin oxi/hydroxy chloride and tin oxides as surface corrosion products. A corrosion mechanism has been proposed.

McCulloch-Pitts neuron structures are comprised of a number of synaptic inputs and a decision element, called soma. In this paper, we propose a 5-bit Graphene Nanoribbon (GNR)-based DAC to fulfill the role of the summation element featuring programmable input weights. The proposed GNR-based 5-bit DAC relies on: (i) GNR unit current cells and (ii) a GNR logic thermometric decoding block. Our implementation is based on mapping the GNR structure's conductance using Matlab and performing the required SPICE analysis using the Matlab based GNR Verilog-A model. The unit current cell geometry and bias conditions were chosen based on the unit cell's conductance map from which we derived its I ON/IOFF ratio, as well as transfer and output characteristics, resembling the classical MOSFET counterpart. By utilizing GNR devices instead of FinFET counterparts, a reduction of the active area of the 5-bit current DAC by up to a factor of three can be achieved. Furthermore, the GNR implementation achieved this while maintaining comparable INL and DNL performance to that of the FinFET variant, i.e., DNL of [-0.196, 0.088] LSB and INL of [-0.809, 0.364] LSB for the proposed GNR 5-bit DAC while operating at a supply voltage of only 0.2 V.