Theoretically speaking, Majority logic, originally proposed in the ^{\prime }70s, enables more compact and efficient arithmetic implementations than the conventional Boolean counterpart. Nonetheless, CMOS technology based Majority logic realizations remain challenging, as standard transistor-based approaches are unable to directly exhibit majority behavior. However, recent exploration on beyond CMOS technologies created a resurgence of the interest in majority logic. In this work, we propose and analyze a novel approach towards the 3-input Majority gate (MAJ3) implementation by means of piezoelectric materials. By leveraging their intrinsic electromechanical properties, we convert the digital input signals into mechanical deformations, which are accumulated in a transfer layer. Subsequently, we transform the combined deformation back to the electric domain with a piezoelectronics element properly designed to perform majority functionality. We first present the underlying principles behind our proposal with a short introduction on majority logic, piezoelectronics, and the utilized simulation framework. Afterwards we introduce the proposed piezoelectric 3-input Majority gate (piezo-MAJ3) and strategies for optimizing its behavior and performance. We also detail the material parameters and structural design impact on device performance by utilizing both analytical discussion and physics-based simulations. Finally, we shortly highlight how our proposal can be directly integrated into CMOS circuits and compare the piezo-MAJ3 potential cost and performance with the ones of state of the art implementations. Our results indicate that when compared with its CMOS counterpart, the piezo-MAJ3 gate requires half the area, it is 7x faster, while reducing with 44% the energy consumption.

In recent years, Spin Waves (SWs) have emerged as a promising avenue for beyond-CMOS computing, offering potential advantages in terms of energy efficiency, scalability, and opening avenues towards novel computation paradigms. Until now, SW interference-based gates, for example, the 3 input majority gate (MAJ3), have been proposed and experimentally demonstrated, and an alternative computing paradigm, which relies on SW phase manipulation instead of SW interference has been proposed. However, state-of-the-art SW-based devices suffer from challenges that hinder the realization of larger-scale SW circuits. In this paper, we explore a different computing avenue that relies on Boolean algebra and introduce a SW Switch that makes use of the Voltage Controlled Magnetic Anisotropy (VCMA) effect to allow/block SW propagation. We introduce the device concept, verify its functionality by means of micromagnetic simulations, and perform a circuit-level analysis on EPFL Combinational Benchmarking Suite circuits. As no SW generation and SW read transducers energy consumption experimental data is available we evaluate their upper bound values for which SW implementations can outperform CMOS counterparts. We implement the circuits by means of state-of-the-art SW technologies and the proposed method, compute the upper bound values, and our results indicate that on average the proposal is increasing the upper bound by about 1.2 ×. Subsequently, we consider SW read transducers energy consumption estimates reported in the literature and argue that while they seem appropriate for evaluating SW Boolean switching gates they have to be multiplied with a factor m>1 to capture the extra complexity of generating the output value for SW interference and Phase manipulation SW gates. Our evaluations indicate that the SW Switch-based approach reduces the energy consumption by 1.2504 × 1.4973 × 1.7443 ×, and 1.9912 ×, when compared to the interference approach, and by 1.2478 ×, 1.4947 ×, 1.7416 ×, and 1.9886 ×, when compared to the phase shifting approach, for m=1.25,1.5,1.75,2, respectively. We finally highlight system level advantages of our proposal and conclude that SW Boolean switching gates are opening the most promising avenue towards energy effective SW computing.

In recent years, Spin Waves (SWs) have emerged as a promising CMOS alternative technology, and SW interference-based majority gates have been proposed and experimentally realized. In this paper, we pursue a different computation avenue and introduce a SW device able to evaluate 2×2 2D convolution, which is a fundamental element for the implementation of Convolutional Neural Networks (CNNs). Assuming that the window pixels are P = [p₁, p₂; p₃, p₄] and the kernel is K = [k₁, k₂; k₃, k₄] we introduce a device which evaluates the convolution result Σ_{i = 1}⁴ p_i k_i within the SW domain by leveraging SWs inherent mechanisms, i.e., information encoding in SW amplitude and phase, SW amplitude decay due to Gilbert damping, SW interference. After introducing the SW device structure we demonstrate its proper behaviour by means of micromagnetic simulations. We also present power consumption, area, and delay estimates and argue that due to the fact that our proposal does not rely on standard adders and multipliers, it can substantially outperform traditional CMOS-based convolution implementations.

Current Spin Wave (SW) state-of-the-art computing relies on wave interference for achieving low power circuits. Despite recent progress, many hurdles, e.g., gate cascading, fan-out achievement, still exist. In a previous work, we introduced a novel SW phase shift based computation paradigm and demonstrated that an n-input Threshold Logic Gate (TLG) can be implemented with n + 1 phase shifters operating on the same SW. In this paper we further develop this concept by introducing a phase shift amount reading method by means of parametric amplification. We make use of 3-input Majority Gate (MAJ3) as discussion vehicle and introduce a novel majority function evaluation approach which postpone the threshold related calculations to the gate output readout stage. Subsequently, we verify this principle by means of micromagnetic simulations and discus the results. Finally, we utilize the proposed MAJ3 gate to implement a collection of representative logic circuits from the EPFL Combinational Benchmarking Suite and evaluate and compare their area, energy consumption, and Energy Area Product (EAP) with the ones of 7 nm CMOS technology node based counterpart imple-mentations. Our estimations indicate that EAP_CMOS/EAP_SW average value is 5.25 and 2.2 for a SW transducer feature size of 20 nm and 30 nm, respectively.