Convolutional Neural Network (CNN) inference has gained a significant amount of traction for performing tasks like speech recognition and image classification. To improve the accuracy with which these tasks can be performed, CNNs are typically designed to be deep, encompassing a large number of neural network layers. As a result, the computational intensity and storage requirements increase dramatically, necessitating hardware acceleration to reduce the execution latency. Field-Programmable Gate Arrays (FPGAs) in particular are well-suited for hardware acceleration of CNN inference, since the underlying hardware can be tailored to rapidly and efficiently perform the required operations. To this end, Xilinx introduced the FINN (Fast, Scalable Quantized Neural Network Inference on FPGAs) framework to leverage FPGAs for Neural Network (NN) inference. The FINN end-to-end deep learning framework converts high-level descriptions of CNN models into fast and scalable FPGA inference accelerator designs that are based on a custom dataflow architecture. In this dataflow architecture the input data are streamed in a feed forward fashion through a pipeline of per-layer dedicated compute units, that each have on-chip access to the associated NN parameters. In order to keep the compute units occupied, specific throughput requirements have to be satisfied by the memory subsystem. These throughput requirements directly dictate the shapes of the on-chip buffers that contain the NN parameter values. Especially for accelerators that exploit a high degree of parallelism, these memory shapes map poorly to the available on-chip memory resources of FPGA devices. As a result, these resources are typically underutilized, which leads an On-Chip Memory (OCM) deficiency, and limits the amount of parallelism that can be exploited. In this thesis, a methodology is proposed that improves the mapping efficiency of NN parameter buffers to the embedded Block RAM (BRAM) resources on FPGAs, without negatively impacting the accelerator throughput. To accomplish this, an architecture is proposed where the memory subsystem and compute units are decoupled, and operate as a producer-consumer system. Within this architecture, the memory subsystem functions at a higher clock frequency relative to the compute units, which enables the memory subsystem to match the consumption rate of the compute units when multiple NN parameter buffers are clustered within the same BRAM instance. Furthermore, a genetic algorithm is used to find optimal group arrangements for these clusters such that the mapping efficiency is improved, and the throughput requirements are still met. The proposed methodology has been applied to a number of CNN accelerators, and demonstrates BRAM reductions of up to 30%. The observed BRAM reductions enable existing FINN accelerator designs to be ported to smaller FPGA devices while maintaining the computational throughput.

Inaccurate and slow positional tracking are fundamental problems of low-cost VR solutions. These factors can induce motion sickness and therefore significantly deteriorate the user experience. There are already a variety of solutions available to track the position of a VR HMD, some of which can be made robust and low-latency by inexpensive means. This thesis proposes a low-cost, outside-in, optical tracking solution. As optical sensor a stationary camera with an IR pass filter is used to capture an array of IR LEDs, which are integrated at strategic locations within the frame of the HMD. By using the OpenCV library the 3D pose of the LEDs can be estimated, and used to change the perspective of the user within the virtual world. In particular, this tracking solution incorporates a fast, cost-effective, modified camera, capable of capturing over 180 frames per second. With this camera and a custom designed polyhedral structure to incorporate the LEDs, the LED array can be calibrated quickly and tracked accurately even when oriented at an obtuse angle with the camera. The high frame rate also allows for a redundancy in pose estimations, obtained by a mix of algebraic and iterative PnP solvers to further improve numerical stability and accuracy. The tracking algorithm accurately tracks the developed prototype at short distances, even when placed in a noisy environment. The calibration procedure can also be performed fast, so that tracking can be resumed within a second when tracking has been lost due to occlusion. Recommendations for further improvements would be to integrate an IMU to provide tracking information in case that the HMD becomes occluded, and to overall improve tracking of rotational movement. Also, a higher resolution optical sensor should be used to improve the range of this tracking solution.