As CMOS scaling approaches the atomic feature size limit which results in a high power density and current leakage, low reliability and increased time and production cost, the need for new materials and devices is increasing. One of the promising materials to replace silicon based devices is graphene nano-ribbons (GNRs) due to its remarkable electronic properties. Theoretical models suggest that 30nm GNR structures can mimic the behaviour of basic Boolean logic gates such as inverter, buffer, or and nor gates while reducing 30x times the propagation delay and using 3000x less gate active area compared to the equivalent CMOS realization. The main goal of this thesis is to fabricate GNR devices that can be ultimately used as building blocks for Boolean logic gates, analyse the limitations of achieving sub-50nm patterns and study the edge termination of the formed GNR patterns. GNR patterns are explored using a simulation model, which can be used for complementary Boolean logic gates. The designed graphene patterns are simulated using tight binding model to calculate the electronic band structure and construct a Hamiltonian matrix. This is followed by calculation of the electronic states and Fermi energies. Non equilibrium Green function (NEGF) models the electrons and holes distribution trough the GNR pattern and the rate at which the charge carriers are transmitted from the source to the drain when they propagate through the device. The result from the NEGF function is used to calculate the charge density using 3D POISSON from which the current through the graphene surface is determined. Finally, with known gate voltages and current, the conductance is found for four different structures in 10 nm and 30 nm technology. By changing the way the structures are connected as pull-up and pull-down network, the behaviour of inverter, buffer, or, and nor gates are obtained. The patterns from the simulation model with 30 nm feature size are used to create a design for devices to be fabricated. In addition, the design includes devices with minimal dimensions from 50 nm to 200 nm, squares, hexagons and pentagons with different dimensions starting from 1 um up to 10 um. For this project, graphene grown by chemical vapour deposition (CVD) was transferred to silicon dioxide samples on which the design of the structures is fabricated. The fabrication process consist of five steps. First, the samples are spin coated with polymethyl-methacrylate (PMMA). Second, electron beam lithography (EBL) is used to pattern the structures, by exposing parts of the resist. Next, the exposed areas are developed in order to remove the resist with introduced damage from the exposure. This is followed by etching the exposed parts of the graphene using oxygen plasma or hydrogen plasma. Finally, the remaining resist is cleaned with acetone. Characterisation of the patterns is performed using Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM). From the Raman measurements it was found that the edge termination is most likely random and defects are introduced to the lattice of the graphene patterns with left contaminants from the polymer. The achieved minimal feature size of the devices is 50 nm, which was confirmed using AFM and SEM. In addition to the morphological characterisation of the samples, electrical measurements are performed and from the transport characteristics, the electron and hole mobilities of mono layer graphene are derived.