A High Voltage (HV) Modular Multilevel Converter (MMC) based Arbitrary Wave shape Generator (AWG) is to be designed for a final voltage of 100 kV with 67 submodules in each arm. They can be used to test unconventional stresses experienced by high voltage equipment. Before the realization of a full-scale prototype setup, it is necessary to validate the controller as it involves the complexity of communication and control of a large number of switches in the circuit while demanding accuracy in the generation of gate pulses. OPAL-RT was identified as a good solution for implementing the MMC control. This thesis intends to investigate two main objectives. Firstly, to evaluate the various capabilities of the OPAL-RT to implement control of MMC by performing simulations and testing it with real MMC with 12- submodules. Secondly, to design a PR controller for the MMC circuit and further validate it in real-time. The topology of MMC, as well as two modulation approaches – Phase-Shifted Carrier (PSC) and Nearest Level Control (NLC) were explored initially. This was followed by the filter design for 50 Hz and 1 kHz fundamental frequencies. Thereafter, the trade-offs for both control strategies based on the filter design requirement were examined. Furthermore, the various software tools included in OPAL-RT were investigated for potential use in the development of the control algorithm. To test the accuracy of gate pulses and the ability to generate precise waveforms for higher fundamental frequencies, Model-in-Loop testing with eFPGAsim is used. By realizing, the control algorithm in the CPU and the MMC in the FPGA, results obtained are compared with the offline simulations. It is observed that the minimum CPU time step is incapable of generating accurate waveforms for higher fundamental frequencies, resulting in missing or delayed gate pulses. Next, the control was implemented in the FPGA using internal PWM generators of the OPAL-RT and the MMC plant was tested both in the FPGA and as actual hardware. In PSC modulation, the phase shift between the upper and lower arm decides the switching pattern of the submodules, contributing to the building of the voltage level at any instant. In this case, the gate pulses’ phase difference between the lower and upper arms are noticed to be larger than what is observed from the offline simulations. These phase delays are resulting in the addition of delayed gate pulses at any instant causing strange switching voltage levels at the output, contributing to unexpected carrier harmonics. Furthermore, because the CPU samples the modulating signal before passing it to the FPGA for processing, it compensates for communication latency while also contributing to inaccuracy. Finally, a PR controller was designed and discretized for performing stability analysis, later implemented on the real-time setup. The PR controller resulted in suppressing the lower order harmonics by reducing them within the expected tolerance limits and the THD obtained was consistent with the results of the offline simulation.