This work introduces a low-power Cortex-M0+ based computing platform for battery-powered, embedded applications. Voltage stacking is used to save power by recycling charge through a power domain between 0V and Vdd, and a power domain stacked on top of it between Vdd and 2Vdd. The technique enables connecting chips of the future directly to the main power source. This increases the power efficiency and the power density of the power delivery scheme. The needed special circuitry components like level shifters and voltage regulators have been designed and integrated into a standard digital SoC flow to demonstrate that voltage stacking can be used for any digital system. For comparison and also functional purposes, the designed system is reconfigurable between the conventional, high throughput, flat mode where all the power- and ground rails are common, and the low power, stacked mode where the power domains are stacked on top of each other. A 1.44µm2 test chip has been fully designed and is to be fabricated in a 40nm CMOS process to evaluate the concept. Pre tape-out simulations show that the power efficiency of the system improves by 15% from 79.5% in the flat mode to 95% in stacked mode, while running a typical benchmark program in the Cortex-M0+ core at 80MHz clock frequency. The system power density for the same test case improves from 10.5mW/mm2 to 34.9mW/mm2. The research has been carried out at NXP Semiconductors in Eindhoven.