We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.@en

Plastic waste increasingly accumulates in the marine environment, but data on the distribution and quantification of riverine sources required for development of effective mitigation are limited. Our model approach includes geographically distributed data on plastic waste, land use, wind, precipitation, and rivers and calculates the probability for plastic waste to reach a river and subsequently the ocean. This probabilistic approach highlights regions that are likely to emit plastic into the ocean. We calibrated our model using recent field observations and show that emissions are distributed over more rivers than previously thought by up to two orders of magnitude. We estimate that more than 1000 rivers account for 80% of global annual emissions, which range between 0.8 million and 2.7 million metric tons per year, with small urban rivers among the most polluting. These high-resolution data allow for the focused development of mitigation strategies and technologies to reduce riverine plastic emissions.

@en