13 records found
1
None
Spur-free all-digital PLL in 65 nm for mobile phones
Spur-free multirate all-digital PLL for mobile phones in 65nm CMOS
Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences
Dynamic bandwidth adjustment of an RF all-digital PLL
Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter
Self-calibration of a Digital Pre-Power Amplifier in a Polar Transmitter
An all-digital offset PLL architecture
Spurious free time-to-digital conversion in an ADPLL using short dithering sequences
A technique to reduce phase/frequency modulation bandwidth in a polar RF transmitter
An EDGE transmitter with mitigation of oscillator pulling
A 0.8 mm^2 all-digital SAW-less polar transmitter in 65 nm EDGE SoC
Elimination of spurious noise due to time-to-digital converter
