This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec pipeline ADC with digital calibration. A foreground ideal calibration test bench has been implemented in MATLAB to correct non-linearities of the amplifier up to the 5th order. A detailed comparison has been made between a class-A amplifier and a class-AB amplifier. Simulation results show that the class-AB amplifier outperforms the class-A amplifier in all performance aspects such as gain, bandwidth, linearity, noise and power consumption, except for the CMRR. A new class-AB amplifier topology has been proposed, which alleviates problems associated with the level shifting capacitors. Due to an insufficient accuracy of the proposed class-AB amplifier in order to save power, the residue output signal from the flip-around MDAC topology becomes distorted. To resolve this problem, the flip-around MDAC has been replaced by a simple charge amplifier MDAC topology. Timing scheme of the pipeline ADC has been modified due to remove the timing related problems and ISI. In addition, layout of the first stage MDAC has been done in TSMC 40nm CMOS technology. Post-layout simulations have shown an excellent Figure-of-Merit (FOM) of 8.08fJ/conv, at an ENOB of 10.8bit and signal bandwidth of 250MHz, which prove that the design is not only energy efficient, but also have a superior speed-resolution product.