A TCAD Simulation Study on the Short-circuit Performance of 650V P-pillar Offset Super-junction MOSFET

Abstract

The limitation of Silicon based power MOSFET was broken by the super-junction (SJ) structure, which can provide lower specific on-resistance and higher breakdown voltage compared with the conventional power MOSFET structure. Multi-epitaxial and multi-ion-implant technology, as a mature manufacturing process of the SJ structure, has been widely used in the field of SJ-MOSFET. Therefore, this process is applied to construct the cell structure of 650V SJ-MOSFET in our study. Based on practical application, high current caused by unexpected short circuit will induce an increasing of the internal temperature of SJ-MOSFET, which leads to an irreversible damage in the SJ-MOSFET devices. However, the short-circuit robustness of SJ-MOSFET is still unstable, and the structure needs to be further improved. In our study, the electrical performance of a 650V SJ-MOSFET with offset P-pillar is theoretically investigated by means of technology computer aided design (TCAD) when the SJ-MOSFET is short circuited. The results clearly show that the optimized SJ-MOSFET can withstand the source-drain voltage of 400V for at least 10 μs in the case of the short-circuit. The thermal distribution and peak temperature of the cell structure of SJ-MOSFET are also simulated to assist in the analysis of the short circuit capable of the device. In addition, the hole current density distribution of two SJ-MOSFETs is considered to gain insight into the effect of P-pillar parameters on the short-circuit robustness. The result represents that the structure with offset P-pillar can effectively improve the short-circuit capability.