Through-substrate cavity fabrication for hybrid wafer-level packaging

Conference Paper (2006)
Author(s)

S Sosin (TU Delft - Old - EWI Ch. Integrated Sensing Devices)

J. Tian (TU Delft - Old - EWI Ch. Integrated Sensing Devices)

L. Wang (TU Delft - Micro and Nano Engineering)

M Bartek (TU Delft - Old - EWI Ch. Integrated Sensing Devices)

Research Group
Old - EWI Ch. Integrated Sensing Devices
More Info
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Publication Year
2006
Research Group
Old - EWI Ch. Integrated Sensing Devices
Pages (from-to)
181-184
ISBN (print)
0-85432-848-3

Abstract

A novel technique for fabrication of through-substrate cavities is proposed and demonstrated on single-crystalline silicon wafers intended for use as a capping substrate in wafer-level packaging. The through-substrate cavities are defined by non-continuous DRIE trenches around the cavity perimeter, where narrow not-etched supporting beams remain to keep the bulk silicon inside cavities. In a subsequent ultrasonic treatment, these beams are broken and cavities are formed. In our experiments, cavities with lateral dimensions from few by few square millimeters down to 250x250 µm2 and supporting beams width of ~10 µm have been reliably cleared using conventional ultrasonic cleaning equipment and a water bath.

Keywords: MEMS packaging, wafer-level packaging, cavity formation, beam fracture, ultrasonic treatment.

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