In this paper, development and characterization of a free-standing electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 µm is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a -8 µm thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.@en

A novel technique for fabrication of through-substrate cavities is proposed and demonstrated on single-crystalline silicon wafers intended for use as a capping substrate in wafer-level packaging. The through-substrate cavities are defined by non-continuous DRIE trenches around the cavity perimeter, where narrow not-etched supporting beams remain to keep the bulk silicon inside cavities. In a subsequent ultrasonic treatment, these beams are broken and cavities are formed. In our experiments, cavities with lateral dimensions from few by few square millimeters down to 250x250 µm2 and supporting beams width of ~10 µm have been reliably cleared using conventional ultrasonic cleaning equipment and a water bath. Keywords: MEMS packaging, wafer-level packaging, cavity formation, beam fracture, ultrasonic treatment.@en