A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow
Zhongkai Wang (University of California)
Minsoo Choi (Samsung Semiconductor)
John Wright (University of California)
Kyoungtae Lee (University of California)
Zhaokai Liu (University of California)
Bozhi Yin (University of California)
Jaeduk Han (Hanyang University)
Sijun Du (TU Delft - Electronic Instrumentation)
Elad Alon (University of California)
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Abstract
We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.