VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

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VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

Conference Paper (2017)

Author(s)

Joost Hoozemans (TU Delft - Computer Engineering)

R. Heij (External organisation)

Jeroen van Straten (TU Delft - Computer Engineering)

Zaid Al-Ars (TU Delft - Computer Engineering)

DOI related publication

https://doi.org/10.1007/978-3-319-56258-2_4 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:1ab2fc93-e275-47c3-9b0c-313bf541919e

More Info

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Publication Year

2017

Language

English

Pages (from-to)

36-43

Publisher

Springer

ISBN (print)

978-3-319-56257-5

ISBN (electronic)

978-3-319-56258-2

Event

ARC 2017: Applied Reconfigurable Computing (2017-04-03 - 2017-04-07), Delft, Netherlands

Downloads counter

167

Abstract

In this paper, we present and evaluate an FPGA acceleration fabric that uses VLIW softcores as processing elements, combined with a
memory hierarchy that is designed to stream data between intermediate stages of an image processing pipeline. These pipelines are commonplace in medical applications such as X-ray imagers. By using a streaming memory hierarchy, performance is increased by a factor that depends on the number of stages (7.5× when using 4 consecutive filters). Using a Xilinx VC707 board, we are able to place up to 75 cores. A platform of 64 cores can be routed at 193 MHz, achieving real-time performance, while keeping 20% resources available for off-board interfacing. Our VHDL implementation and associated tools (compiler, simulator, etc.) are available for download for the academic community.