VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

Conference Paper (2017)
Author(s)

Joost Hoozemans (TU Delft - Computer Engineering)

R. Heij (External organisation)

J. van Straten (TU Delft - Computer Engineering)

Zaid Al-Ars (TU Delft - Computer Engineering)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1007/978-3-319-56258-2_4
More Info
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Publication Year
2017
Language
English
Research Group
Computer Engineering
Pages (from-to)
36-43
ISBN (print)
978-3-319-56257-5
ISBN (electronic)
978-3-319-56258-2

Abstract

In this paper, we present and evaluate an FPGA acceleration fabric that uses VLIW softcores as processing elements, combined with a
memory hierarchy that is designed to stream data between intermediate stages of an image processing pipeline. These pipelines are commonplace in medical applications such as X-ray imagers. By using a streaming memory hierarchy, performance is increased by a factor that depends on the number of stages (7.5× when using 4 consecutive filters). Using a Xilinx VC707 board, we are able to place up to 75 cores. A platform of 64 cores can be routed at 193 MHz, achieving real-time performance, while keeping 20% resources available for off-board interfacing. Our VHDL implementation and associated tools (compiler, simulator, etc.) are available for download for the academic community.

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