Dynamic reconfiguration of hardware accelerators using Partial Reconfiguration

Abstract

Field-programmable gate arrays (FPGAs) have become larger, and that increases the time needed to load their configuration from flash memory. This is a problem for FPGAs that communicate over PCI Express (PCIe) because the standard requires an endpoint device to respond within 120 ms of power-on.

This thesis investigates whether partial reconfiguration can offer a solution to this PCIe timing requirement. The Tandem configuration technique that is available for AMD FPGAs was tested, and its performance was evaluated using a measurement system that monitored both the PCIe link and the partial reconfiguration.

Tandem configuration, specifically Tandem PCIe, was determined to be the most effective solution to make sure the PCIe link on a large FPGA comes online within the 120 ms PCIe timing requirement, even when compared to other solutions not using partial reconfiguration. Partial reconfiguration on top of Tandem PCIe was tested and its performance was measured. The default pathway of using the Media Configuration Access Port (MCAP) to perform the partial reconfiguration was found to be too slow (under 3 MB/s) for most dynamic partial reconfiguration workloads.

A study was done to see how high partial reconfiguration rates can be pushed in hypothetical future FPGAs. It is concluded that, with careful design, reconfiguration rates of up to 400 GB/s are feasible. These rates were then applied to two case studies to see how much dynamic partial reconfiguration workloads can benefit from higher configuration rates. This analysis showed that for some workloads higher reconfiguration rates keep lowering the total runtime, but that an asymptote is reached eventually when the computation time becomes the bottleneck instead of the reconfiguration time.