Dynamic Hardware Binary Translator for ρ-VEX

Abstract

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor mostly developed on FPGAs. On the other hand, popular embeddedarchitectures include the established ARM architecture and the newly rising RISC-Varchitecture. In order for these architectures to communicate with theρ-VEX core, atranslation procedure has to be established. In this thesis, a hardware dynamic binarytranslator was designed, able to translate on-the-fly ARM and RISCV instructions toρ-VEX instructions. The translator will enable heterogeneous platforms to be developedand also allow pre-compiled binaries for one (ARM/RISC-V) architecture to be directlyported in another one (ρ-VEX). This thesis provides a design process that focuses ontwo approaches: first is the minimization of the overhead resulting from the transla-tion procedure, and the second is the minimization of the hardware alterations and/orhardware additions. These design choices were examined in theρ-VEX core simulator.The simulations show that for overhead minimization, the resulting overhead can be aslow as 1% for the RISC-V with focusing on the overhead minimization, and as high as1024% with ARM and hardware minimization in mind.