Design for Reliability of Wafer Level MEMS packaging

Abstract

The world has seen an unrivaled spread of semiconductor technology into virtually any part of society. The main enablers of this semiconductor rush are the decreasing feature size and the constantly decreasing costs of semiconductors. The decreasing costs of semiconductors in general are caused by the smaller feature size, the higher yield and larger production volumes. This has made products containing semiconductors cheaper in production thus reaching a larger market. The smaller feature size enables more computing power in the same volume creating new markets and growing application areas. The increasing number of appliances using semiconductor components is also driving the fast growth of the market. The trend of miniaturization of electronic components also demands the miniaturization and integration of non-electrical functions to allow for large decreases in size, weight and possibly cost. Soon after the first semiconductors were developed the first Micro Electrical Mechanical Systems (MEMS) were also created. In the 1960’s and 1970’s experiments with MEMS were done in lab environments. MEMS technology can be used to miniaturize non-electrical components thus enabling further system shrinkage and increased function density. The technologies, experiments and numerical simulations in this thesis provide MEMS designers with a design guideline in the creation process of new Wafer Level Thin Film Package (WLTFP) products as well as an overview of the most likely failure modes and high risk processes in the assembly. WLTFP’s are a miniature batch-process and wafer scale encapsulation method for MEMS that need space to move or hold a certain amount of gas. In the first chapters an overview of the most important processing steps in the production of WLTFP’s and the subsequent assembly steps needed to form a plastic encapsulated package is presented. Most common assembly steps included: wafer thinning, chip singulation, die-attach, wire bonding, overmoulding and saw, trim, mark & form. Wafer thinning is necessary to thin the chip to such a thickness that it will fit into the desired package. Chip singulation or dicing is commonly done by a diamond blade saw and makes separates the wafer into individual chips. Die-attach is the placement of the chip onto the carrier, for example a lead frame, by means of a glue. After dieattach connection the IO of the chip to the carrier can be done by wirebonding. After wire-bonding the package is overflowed by epoxy moulding compound to protect the chip inside from the environment. After finishing the package and marking it one has a complete product. In the creation process of a new MEMS product the design team is faced with a multi-scale, multi-physics and multi-timescale challenge. Nanometer dimensions can impact a millimeter size product and hours of operation can change a MEMS that performs microsecond measurements. To address this challenge an integrated design process is needed that covers the chip and wafer design as well as the package and all of the intermediate processes. An example of the influences from the package on the chip is calculated and shown in chapter three. In chapter four the properties of thin layers are investigated. In this investigation copper thin film are deposited on freestanding micro cantilevers. The samples are analyzed with white light interferometry to obtain the initial geometry properties and cantilever warpage. Using electrostatic pull-in to pull down the cantilever to the substrate the pull-in voltage is obtained. The stiffness of the two layer system can be derived from the pull-in voltage. Copper film thicknesses of 10 and 50 nanometer are measured and a size-dependant stiffness is proven. During the assembly of a WLTFP several failure modes are found. In the wafer thinning process the application of wafer thinning tape to the active side of the wafer can easily break many WLTFP’s. This can happen during the application or for example the removal of the tape. The placement of the wafer on dicing foil is also a potential risk as it leaves the MEMS exposed to the water jet of the dicing machine. Wire-bonding can be hazardous to MEMS sensitive to resonance, this risk can relatively easy be mitigated by calculation of eigenmodes and eigenfrequencies. The overmoulding process and the associated process pressure can be hazardous to for example membranes or large WLTFP’s due to the static pressure on the cavity. The numerical simulations developed in chapter five provide a toolbox to check for weak spots in the design and investigate changes by virtual prototyping instead of physical prototyping. The simulations also include wafer foil application and removal simulation. The use of cohesive zones allows for a detailed investigation of the loads on the WLTFP. In chapter six the interface properties of the wafer thinning foil are investigated by means of a peeling experiment combined with numerical simulations. The characterization method yields interface properties that serve as input for aforementioned numerical simulations. The Design of Experiments presented in chapter seven investigates the influence four major design choices on the likelihood of survival during assembly. The span of the WLTFP, the corner rounding radius, cap thickness and presence of a pillar are investigated. After all 18720 samples were evaluated a design guidelines was derived. The design guideline in combination with the numerical simulations provides the MEMS design community with tools during the chip-design stage. This aids to the integrated approach of designing new MEMS and reduces the time to market and number of design iterations needed.