Addressing large-scale qubit arrays for quantum computer

Abstract

The recent implementation of single electron quantum dots (QDs) in semiconductor hetero-structures as quantum bits (Qbits) [1] disclosed a promising route for the forthcoming creation of the first quantum computers based on a large set of Qbits. The scaling up of Qbits would indeed exhibit the full potential of quantum computation. Confinement of electrons in QDs takes place at cryogenic temperatures by applying specific constant voltages to the gates of the QD [1]. The goal of this thesis has been the design and the analysis of a circuit providing constant voltages, with accuracy of 5 ?V, to a set of 768 QDs kept at 20 mK. The proposed circuit would supply up to 2304 different voltages (3 biases/QD) employing only one DC bias, thus minimizing the thermal power dissipated into the cryogenic environment. Each Qbit is biased to its specific voltage (between -1 V and 1 V with accuracy of 5 ?V) by dedicated capacitors. The charge stored in a capacitor is dynamically maintained around a constant value by the charging-discharging cycle driven by a MOSFET switch. The input controlling each switch, in turn, is managed by a digital devices assembly, which coordinates the 2304 different cycles. This part of the circuit is in contact with the Qbits matrix only through demultiplexers; therefore it does neither interfere with the cryogenic environment nor with the delicate coherent states of the Qbits. The experimental section of this thesis focused on the fabrication and the characterization at room temperature and 4.2 K of MOS and parallel plate capacitors with thin (30 nm) SiO2 film. The measured capacities for the smallest area capacitors have a value of 6.6 pF. While, the mean leakage current density through the oxide layer between -1 V and 1 V is at most 6 nA/cm2. The average leakage current density at 4.2 K, between -10 V and 10 V, is 4 nA/cm2 for the smallest MOS capacitors. This observation proved that the structural integrity of the capacitors is preserved at extremely low temperatures. The quantitative analysis of the analog circuit dedicated to the charging-discharging cycles showed that a MOSFET switching frequency of 38 MHz is sufficient for the operation with 6.6 pF capacitor connected in series with 1 G? resistor. Moreover, the circuit stability analysis revealed that the system has a good resilience against random fluctuations of several variables. The results obtained in this work help us to sketch the future outlook to create a complete and efficient driving circuitry for large scale single electron Qbits computers.