System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
Conference Paper
(2013)
Author(s)
K. Chandrasekar (TU Delft - Computer Engineering)
C Weis (External organisation)
Benny Akesson (External organisation)
N Wehn (External organisation)
K.G.W. Goossens (TU Delft - Computer Engineering)
Research Group
Computer Engineering
DOI related publication
https://doi.org/10.7873/DATE.2013.061
To reference this document use:
https://resolver.tudelft.nl/uuid:33acdece-258b-4a3c-8c0f-a7b8cee91d4a
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Publication Year
2013
Language
English
Research Group
Computer Engineering
Pages (from-to)
236-241
ISBN (print)
978-3-9815370-0-0
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