A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

Conference paper (2019)

Authors

P. Cenci Electronic Instrumentation - EEMCS
M. Bolatkale NXP Semiconductors, Electronic Instrumentation - EEMCS
Robert Rutten NXP Semiconductors
M. Ganzerli NXP Semiconductors
K.A.A. Makinwa Microelectronics
L Breems NXP Semiconductors
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2019 P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K.A.A. Makinwa, Lucien Breems
DOI
help_outline
https://doi.org/10.23919/VLSIC.2019.8778176
More Info
expand_more

Published Date

2019

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

Files

08778176.pdf
(.pdf | 0.354 Mb)