A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS
P. Cenci (TU Delft - Electronic Instrumentation)
M. Bolatkale (TU Delft - Electronic Instrumentation, NXP Semiconductors)
R. Rutten (NXP Semiconductors)
M. Ganzerli (NXP Semiconductors)
G. Lassche (Catena)
K. Makinwa (TU Delft - Microelectronics)
Lucien Breems (NXP Semiconductors)
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Abstract
This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.