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A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

Conference Paper (2019)
Author(s)

P. Cenci (TU Delft - Electrical Engineering, Mathematics and Computer Science)

M. Bolatkale (TU Delft - Electrical Engineering, Mathematics and Computer Science, NXP Semiconductors)

R. Rutten (NXP Semiconductors)

M. Ganzerli (NXP Semiconductors)

G. Lassche (Catena)

K. Makinwa (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Lucien Breems (NXP Semiconductors)

Research Group
Electronic Instrumentation
DOI related publication
https://doi.org/10.23919/VLSIC.2019.8778176 Final published version
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Publication Year
2019
Language
English
Research Group
Electronic Instrumentation
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Article number
8778176
Pages (from-to)
C230-C231
Publisher
IEEE
ISBN (print)
978-1-7281-0914-5
ISBN (electronic)
978-4-86348-720-8
Event
2019 VLSI (2019-06-09 - 2019-06-14), Kyoto, Japan
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381
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Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

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