ARDAPL
An Adaptive Resilient Data-Plane for Stateful Packet Processing
Chenxing Ji (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Adrian Zapletal (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Fernando Kuipers (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
Stateful network functions on programmable switches make decisions within microseconds by directly operating on in-switch state. However, their performance hinges on the availability and correctness of the state stored in scarce on-chip memory. When a switch failure occurs, fast reroute can restore connectivity, but the rerouted traffic loses access to the existing state, causing incorrect network behavior. In extreme cases, packets may no longer be forwarded. Given switch constraints and bandwidth overhead, maintaining synchronous backups of all states across all nodes is practically infeasible. Moreover, existing recovery mechanisms typically incur high latency. In this paper, we present ARDAPL, a framework that leverages unallocated hardware resources to achieve in-data-plane failover at the μs-scale. We have prototyped ARDAPL on Tofino switches and evaluated its impact on existing traffic. Our experimental results show that less than 0.002% of traffic was affected over the entire failure period, and ARDAPL can achieve sub-50μs failover time while incurring 5μs latency.
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File under embargo until 30-12-2026