An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM
Laurens van Dam (Student TU Delft)
Johan Peltenburg (TU Delft - Computer Engineering)
Zaid Al-Ars (TU Delft - Computer Engineering)
H. Peter Hofstee (IBM Austin Research Laboratory)
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Abstract
The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.