An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM

Conference paper (2019)

Authors

Laurens van Dam Student

J.W. Peltenburg Computer Engineering -

Z. Al-Ars Computer Engineering -

H.P. Hofstee IBM Austin Research Laboratory

Research Group

Computer Engineering () (TU Delft)

DOI: https://doi.org/10.1145/3316279.3316284

FPGA Unum Accelerator Posit Arithmetic BLAS OA-Fund TU Delft Decimal accuracy Pair-HMM Unum-III

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Published Date

2019

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

The newly proposed posit number format uses a significantly different approach to represent floating point numbers. This paper introduces a framework for posit arithmetic in reconfigurable logic that maintains full precision in intermediate results. We present the design and implementation of a L1 BLAS arithmetic accelerator on posit vectors leveraging Apache Arrow. For a vector dot product with an input vector length of 10^6 elements, a hardware speedup of approximately 10^4 is achieved as compared to posit software emulation. For 32-bit numbers, the decimal accuracy of the posit dot product results improve by one decimal of accuracy on average compared to a software implementation, and two extra decimals compared to the IEEE754 format. We also present a posit-based implementation of pair-HMM. In this case, the hardware speedup vs. a posit-based software implementation ranges from 10^5 to 10^6. With appropriate initial scaling constants, accuracy improves on an implementation based on IEEE 754.

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