A High-speed Amplifier And Loop Filter Architecture For A GHz Sampling Sigma-Delta ADC

Master thesis (2018)

Authors

X. Zhan Electrical Engineering, Mathematics and Computer Science

Contributors

F. Sebastiano (supervisor 1)
M. Bolatkale (supervisor 1)
P. Cenci (supervisor 1)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2018 Xin Zhan
ADC Sigma Delta Loop filter
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Published Date

21-09-2018

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

This thesis presents the design and implementation of a low power 3rd-order loop filter and a low power, compact, high-speed inverter-based amplifier designed in 28nm HPC for a GHz sampling Σ∆ modulator.
In the earlier design, the size of the pMOS in an inverter was found to be nine times larger than the nMOS which is not practical to obtain a compact design.
The proposed 4by4 inverter structure in a kind of matrix form achieves a gain of minimum 25dB and maximum 28dB at the worst corner and best corner without loading resistor respectively. The designed inverter amplifier is found to be relatively tolerant over PVT without an LDO. The simulation of the modulator system is implemented with an ideal quantizer and resistive DAC. The simulation results of the modulator shown an ENOB of 10bits with 0.41mW power consumption in the worst case and an ENOB of 10.7bits with 0.53mW power consumption in the best case.