Design and Realization of a Digital Baseband Subsystem of Wakeup Receiver for Wireless Sensor Networks

Abstract

In the development of wireless sensor networks, the lifetime of a sensor node is always a key design consideration. Since the battery in a sensor node can usually not be recharged or changed, power management is an effective way to extend the network lifetime. The wireless transceiver, also regarded as the ‘main radio’, is a relatively power hungry component in a sensor node. Therefore, an auxiliary always-on hardware ‘wakeup radio’ was proposed in order to reduce the overall power consumption. The wakeup radio listens to the wireless channel whereas the main radio is only active for a rather short time when the wakeup radio receives the packet with a certain pattern. Consequently, the power efficiency becomes a primary concern in the design of wakeup radio. This thesis focuses on the low power design and implementation of a digital baseband subsystem in the wakeup radio. Firstly, the architecture and details of the subsystem are described. Then the design is verified by both a Spartan-3 FPGA board and TSMC90 chips. The design is functional as designed. In the end, the chip measurement setup and results are discussed. The power consumption varies from 2.1 ?w to 8.4 ?w, within our design target of 10 ?w. To our knowledge, it is the first work on the digital implementation and chip measurement of the wakeup radio.