A split transconductor high-speed SAR ADC
Conference Paper
(2015)
Author(s)
Dante Gabriel Muratore (Università di Pavia)
Edoardo Bonizzoni (Università di Pavia)
Franco Maloberti (Università di Pavia)
DOI related publication
https://doi.org/10.1109/ISCAS.2015.7169176
Final published version
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Publication Year
2015
Language
English
Article number
7169176
Pages (from-to)
2433-2436
ISBN (electronic)
9781479983919
Event
Downloads counter
133
Abstract
A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.