A split transconductor high-speed SAR ADC

Conference paper (2015)

Authors

D.G. Muratore Pavia University

Edoardo Bonizzoni Pavia University

Franco Maloberti Pavia University

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Published Date

2015

Language

English

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Abstract

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.