Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

Conference paper (2018)

Authors

C. Porret IMEC
A. Hikavyy IMEC
E. Rosseel Kavli institute of nanoscience Delft
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J. F. Gomez Granados IMEC, Katholieke Universiteit Leuven
S. Baudot IMEC
A. Vohra Katholieke Universiteit Leuven
B. Kunert IMEC
B. Douhard IMEC
A. Sammak Kavli institute of nanoscience Delft, QuTech Advanced Research Centre
G. Scappucci QCD/Scappucci Lab - QuTech Advanced Research Centre , QuTech Advanced Research Centre, Kavli institute of nanoscience Delft
Research Group
QCD/Scappucci Lab (QuTech Advanced Research Centre) (TU Delft)
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Published Date

2018

Language

English

Reuse Rights

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Faculty

QuTech Advanced Research Centre

Department

Quantum Computing Division

Research Group

QCD/Scappucci Lab

Abstract

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.