A multiphase, fast-settling, low-jitter and low-power frequency synthesizer for brain-machine interface telemetry

Abstract

Wireless telemetry in distributed brain-machine interface requires high data throughput and aggressive duty-cycling to minimize power consumption and tissue heating. Scaling these systems to multi-node implant networks places stringent demands on the underlying frequency synthesizers, particularly requiring ultra-fast settling time and accurate multiphase output for advanced modulation schemes under strict power and area constraints.


To address these requirements, this dissertation presents a multiphase, fast-settling, low-jitter and low-power frequency synthesizer tailored for wireless neural implant networks. Designed for the ultra-wideband from 3 to 10 GHz, the synthesizer operates across channels centered at 3, 4, and 5 GHz. The proposed architecture features a dual-loop design comprising a digital coarse-tuning loop that employs an adaptive successive approaching register search algorithm, and a fine-tuning loop utilizing a fast-settling type-I phase-locked loop.


The proposed dual-loop synthesizer is designed to be implemented in 65 nm CMOS technology and occupies an active area of 0.052mm2. Driven by a 500 MHz reference clock, the design has been validated through comprehensive post-layout simulations. It achieves a rapid settling time of below 150 ns, which allows for aggressive duty-cycling to significantly reduce average power consumption. The synthesizer successfully generates eight output phases to support 8PSK with an optimal rms jitter of 559 fs and a phase noise of -124 dBc/Hz at a 1 MHz offset. At the 3 GHz operating channel, the system consumes 2.65 mW of power, yielding a jitter-power FoM of -240.8 dB. Compared to state-of-the-art designs, the proposed synthesizer significantly improves the settling time without compromising the jitter-power trade-off.