A 10Gb/s PI-CDR design
Master Thesis
(2023)
Author(s)
A. Gardouh (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Contributor(s)
M. S. Alavi – Mentor (TU Delft - Electronics)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright
© 2023 Aschraf Gardouh
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Publication Year
2023
Language
English
Copyright
© 2023 Aschraf Gardouh
Graduation Date
26-06-2023
Awarding Institution
Delft University of Technology
Programme
['Computer Science']
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract
In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.