A 10Gb/s PI-CDR design

Master thesis (2023)

Authors

A. Gardouh Electrical Engineering, Mathematics and Computer Science

Contributors

S.M. Alavi Electronics - EEMCS (supervisor 1)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Aschraf Gardouh
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Published Date

26-06-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.