Design of large-area metasurfaces for the mid-IR and suited for CMOS-compatible fabrication by masked lithography

Abstract

The use of masked UV (i-line) lithography in a MEMS foundry for CMOS-compatible fabrication of large-area metasurface-based absorbers for the mid-infrared is demonstrated. The challenges are in: (a) the limited number of acceptable metals, (b) the thickness tolerance of the layers used in the CMOS process, and (c) the imaging capabilities of i-line lithography as compared to e-beam. The claimed throughput advantage with manageable distortion of masked lithography and the suitability of the layers used in a CMOS-compatible process in the fabrication of mid-IR absorbers was tested. Issues investigated are: (a) the impact of aluminium as the preferred metal in the MIM patch on the plasmonic response, (b) the influence of SiO2 as preferred dielectric material, (c) the effect of corner rounding and horizontal-vertical bias of the masked lithography and (d) measures that can be taken during the design phase to mitigate any such detrimental effect. Based on the findings, disk-shaped patches are identified as the most suitable for shape-tolerant design. Metasurfaces with a unit-cell side-length of 3μm were fabricated over a chip area larger than 105μm2. Measurements do confirm that (a) aluminium is a suitable CMOS-compatible material for mid-IR metamaterial absorber fabrication, (b) a large surface roughness results in widening of the absorption peaks and (c) the typical layer thickness tolerance used in a MEMS foundry is also acceptable for mid-IR metasurface fabrication. Masked lithography limits the minimum design wavelength to about 3.5μm, while the surface roughness Rq ~ 5nm results in a bandwidth up to FWHM = 400nm.