Scheduling in high performance buffered crossbar switches
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Abstract
High performance routers are the basic building blocks of the Internet. Most high performance routers built today use crossbars and a centralized scheduler. Due to their high scheduling complexity, crossbar-based routers are not scalable and cannot keep pace with the explosive growth of the Internet. This dissertation studies a slight variation to the crossbar, a buffered crossbar switching architecture. A scalable buffered crossbar switch design is proposed, using embedded unicast scheduling. Furthermore, an efficient buffered crossbar-based switching architecture is described for multicast traffic support as well as the integration of unicast and multicast traffic flows. Finally, a partially buffered crossbar switching architecture is proposed. This architecture is shown to exhibit high performance, comparable to that of fully buffered crossbars, and a low cost, comparable to that of unbuffered crossbars.