Developing Gate Drivers with Ultra-FastShort-Circuit Detection for High Performance Semiconductor Technology

Master Thesis (2020)
Author(s)

P. Tiftikidis (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

Thiago Soeiro – Mentor (TU Delft - DC systems, Energy conversion & Storage)

P. Bauer – Graduation committee member (TU Delft - DC systems, Energy conversion & Storage)

A. Lekic-Vervoort – Graduation committee member (TU Delft - Intelligent Electrical Power Grids)

Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright
© 2020 Panagiotis Tiftikidis
More Info
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Publication Year
2020
Language
English
Copyright
© 2020 Panagiotis Tiftikidis
Graduation Date
21-10-2020
Awarding Institution
Delft University of Technology
Programme
['Electrical Engineering | Sustainable Energy Technology']
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

The last ten years with the entrance of the SiC devices at the power electronics industry, new fundamental requirements have emerged. New types of gate drivers need to be developed due to the need for creating two voltage levels for driving the SiC based power switches efficiently; one positive and one negative bias voltage. Besides this requirement, extra measures need to be taken for the proper operation of the driver and its sufficient protection. The electromagnetic interference is increased compared with the conventional silicon based applications, which potentially can cause malfunction or disruption at the operation of the gate driver. Furthermore, ultra-fast response in case of faults must be designed, because of the lower fault capability of the new devices. Sophisticated methods are employed with the measurement of di/dt being one of them. This work focuses on proposing, designing, and testing of a robust gate driver capable of detecting and isolating in less than 1 μs a short-circuit of a power module. It uses the PCB principle embedded Rogowski coil so that the gate driver control can re-build a voltage signal, which is an image of the current flowing through the upper and bottom active switches. Finally, a comparison band logic interrupts the gate ON signal when the current reaches a prohibitive level. Simulation and experimental tests are used to verify the advantages of the proposed gate driver.

Files

Final_thesis_report.pdf
(pdf | 12.3 Mb)
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