Multilayer VLSI layout for interconnection networks
Conference Paper
(2000)
Author(s)
CH Yeh (External organisation)
EA Varvarigos (TU Delft - Computer Engineering)
B Parhami (External organisation)
Research Group
Computer Engineering
To reference this document use:
https://resolver.tudelft.nl/uuid:71d5d738-bfd5-4388-9fee-0d047003f53f
More Info
expand_more
expand_more
Publication Year
2000
Research Group
Computer Engineering
Pages (from-to)
33-40
ISBN (print)
0-7695-0768-9
No files available
Metadata only record. There are no files for this record.