Characterization of a RISC-V Microcontroller Through Fault Injection

Conference paper (2020)

Authors

Dario Asciolla Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier LIRMM
Luigi Dilillo Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier LIRMM
D. Santos University of Vale do Itajaí
Douglas Melo University of Vale do Itajaí
A. Menicucci Space Systems Egineering
Marco Ottavi University of Rome Tor Vergata
Research Group
Space Systems Egineering
RISC-V Simulation Fault injection Micronontroller
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Published Date

2020

Language

English

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Research Group

Space Systems Egineering

Abstract

This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simulation based on Modelsim and targets a set of 1000 fault injected per microcontroller block and per benchmarck. The chosen benchmarks are the Dhrystone and CoreMark that may represent generic workloads. The results show certain block are more prone to fault than others, as also confirmed by a vulnerability analysis that correlates the number of observed faults and the rate of access to the blocks.