Model Stacking Performance Comparisons for Lifetime Estimation of CMOS ICs

Abstract

Integrated circuits are vital in the modern world. Testing these circuits is often a months long process involving measurements at multiple times during long stress tests. In this work, final measurements from such tests are predicted based on early measurements, potentially reducing the time needed for such tests and giving preliminary results. In addition to this problem, research is done into the benefits of model stacking ensambles, and around the performance impact of using a low bit precision. From our experiments, we observe a significant performance improvement when using model stacking variations. We also find that model stacking retains its performance better than all other tested models when using a lower bit precision.