Linearity analysis of a CMOS image sensor

Abstract

In this paper, we analyze the causes of the nonlinearity of a voltage-mode CMOS image sensor, including a theoretical derivation and a numerical simulation. A prototype chip designed in a 0.18 μm 1-poly 4-metal CMOS process technology is implemented to verify this analysis. The pixel array is 160 × 80 with a pitch of 15 μm, and it contains dozens of groups of pixels that have different design parameters. From the measurement results, we confirmed these factors affecting the linearity and can give guidance for a future design to realize a high linearity CMOS image sensor.