Linearity analysis of a CMOS image sensor

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Linearity analysis of a CMOS image sensor

Conference Paper (2017)

Author(s)

Fei Wang (TU Delft - Electronic Instrumentation)

Albert J.P. Theuwissen (TU Delft - Electronic Instrumentation, Harvest Imaging)

CMOS image sensor Linearity Voltage mode

DOI related publication

https://doi.org/10.2352/issn.2470-1173.2017.11.imse-191 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:89d8024d-8ae2-4418-a140-5aa73ec33d21

More Info

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Publication Year

2017

Language

English

Pages (from-to)

84-90

Event

Downloads counter

168

Abstract

In this paper, we analyze the causes of the nonlinearity of a voltage-mode CMOS image sensor, including a theoretical derivation and a numerical simulation. A prototype chip designed in a 0.18 μm 1-poly 4-metal CMOS process technology is implemented to verify this analysis. The pixel array is 160 × 80 with a pitch of 15 μm, and it contains dozens of groups of pixels that have different design parameters. From the measurement results, we confirmed these factors affecting the linearity and can give guidance for a future design to realize a high linearity CMOS image sensor.