This article reviews nearly 60 years of solid-state image sensor evolution and identifies potential new frontiers in the field. From early work in the 1960s, through the development of charge-coupled device image sensors, to the complementary metal oxide semiconductor image sensors now ubiquitous in our lives, we discuss highlights in the evolutionary chain. New frontiers, such as 3D stacked technology, photon-counting technology, and others, are briefly discussed.

This paper presents a new 2-step SAR ADC architecture for image sensors in machine vision applications. This structure effectively improves the structural problems of the image sensor caused by the area occupied by the ADC, such as linearity and temporal noise performance. In this work, we designed a two-step SAR ADC using a 6-bit SAR ADC and a PGA generating residue and offset. Since the number of unit capacitor's is reduced, the common centroid method is applied in the capacitor layout to improve the linearity. As a result, the capacitor mismatch characteristic is improved, and the differential nonlinearity (DNL) obtained is +0.36/-0.28LSB. In addition, the temporal noise is about 530 μ Vrns due to the small bandwidth of the column-parallel structure in an image sensor. The implemented ADC achieves 250 kS/ s as a maximum speed. The maximum frame rate of the sensor is 2500fps. The power consumption of the sensor, except for the LVDS interface, is 37.5 ∼mW. This sensor is designed in TowerJazz CIS 180 ∼nm process with one poly and four metal layers. The supply voltage of the analog and digital domains are 3.3 ∼V and 1.8 ∼V, respectively.

This paper presents a novel technique for dark current compensation of a CMOS image sensor (CIS) by using in-pixel temperature sensors (IPTSs) over a temperature range from −40 °C to 90 °C. The IPTS makes use of the 4T pixel as a temperature sensor. Thus, the 4T pixel has a double functionality, either as a pixel or as a temperature sensor. Therefore, the dark current compensation can be carried out locally by generating an artificial dark reference frame from the temperature measurements of the IPTSs and the temperature behavior of the dark current (previously calibrated). The artificial dark current frame is subtracted from the actual images to reduce/cancel the dark signal level of the pictures. In a temperature range from −40 °C to 90 °C, results show that the temperature sensors have an average temperature coefficient (TC) of 1.15 mV/°C with an inaccuracy of ±0.55 °C. Parameters such as conversion gain, gain of the amplifier, and ADC performance have been analyzed over temperature. The dark signal can be compensated in the order of 80% in its median value, and the nonuniformity is reduced in the order of 55%.

This article focuses on the parasitic light sensitivity (PLS) of a commercially available CMOS camera with a global shutter (with a storage node in the charge domain) and shared pixel architecture. The PLS is characterized as a function of both the wavelength and the incident angle of the incoming light. The measurement results are linked to the layout of the pixels to understand and explain the obtained characterization data.

This article focuses on the angular dependency of the light sensitivity of a commercially available CMOS camera with a global shutter (storage node (SG) in the charge domain) and shared pixel architecture. The angular dependency is characterized as a function of both the wavelength and the angle of incidence of the incoming light. The measurement results are linked to the layout of the pixels as a means to explain the obtained characterization data.

A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

This letter introduces a Gm-cell-based CMOS image sensor (CIS) achieving deep subelectron noise performance. The CIS presents a new compensation block and low-noise current source to improve the performance of the Gm pixel. Furthermore, an optional first-order IIR filter is implemented to improve the output swing. The conversion gain, full well capacity, and dynamic range of the CIS can be easily adjusted by the charging time and the filter mode for different applications. The prototype chip is fabricated in a standard 180 nm CIS process and has a deep subelectron read noise of 0.31e-rms at minimum (of the noise distribution) and 0.42e-rms at peak (of the noise distribution). A smooth and clear photon-counting histogram is observed.

One of the fastest growing markets in the semiconductor industry is being driven by businesses in the solid-state imaging sector. An overview of the world-wide CIS (CMOS Image Sensor) market is illustrated in Figure 1.4.1. The actual CAGR (compound annual growth rate) from 2010 until 2019 was 15.2% in units and 16.9% in sales, while the forecasted CAGR from 2019 until 2024F is 11.5% in units and 7.2% in sales. Existing DRAM fabrication facilities are being converted into CIS manufacturing plants to cope with the increasing demand for CMOS image sensors [1]. Despite a small 4% drop in revenue, and nearly flat unit growth due to the disruptions caused by COVID-19 in 2020, in 2024F the CIS sector expects a record high of 26.1B and 11B units/year [2]. A simple calculation shows that over the course of 2020 (6.3B units, 18.2B), globally 200 image sensors are being produced every second at an average price of 2.9. Realizing this scale of production by the end of 2020 will require a total of 5.4M wafers (300mm diameter), which is equivalent to a silicon area of 76 soccer fields!

This article presents in-pixel (of a CMOS image sensor (CIS) temperature sensors with improved accuracy in the spatial and the temporal domain. The goal of the temperature sensors is to be used to compensate for dark (current) fixed pattern noise (FPN) during the exposure of the CIS. The temperature sensors are based on substrate parasitic bipolar junction transistor (BJT) and on the nMOS source follower of the pixel. The accuracy of these temperature sensors has been improved in the analog domain by using dynamic element matching (DEM), a temperature independent bias current based on a bandgap reference (BGR) with a temperature independent resistor, correlated double sampling (CDS), and a full BGR bias of the gain amplifier. The accuracy of the bipolar based temperature sensor has been improved to a level of ±0.25 °C, a 3σ variation of ±0.7 °C in the spatial domain, and a 3σ variation of ±1 °C in the temporal domain. In the case of the nMOS based temperature sensor, an accuracy of ±0.45 °C, 3σ variation of ±0.95 °C in the spatial domain, and ±1.4 °C in the temporal domain have been acquired. The temperature range is between-40 °C and 100 °C.

This paper presents a CMOS image sensor (CIS) with a zoom ADC, to quantize in-pixel temperature sensors, as well as for faster readout speed of the image pixels while maintaining low quantization noise. The proposed 15 bit zoom ADC has a 4 bit Unit Capacitor Array (UCA) SAR and a 13 bit incremental 2^nd-order delta-sigma ADC (DSADC), as its first and second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. Measurement results on 4 chips show the proposed zoom ADC could operate at least twice as fast, when maintaining the same signal-to-noise ratio (SNR), or improve its SNR by 9 dB, when maintaining its sampling speed, compared to a DSADC only alternative. The proposed 15 bit ADC is measured a SNR of 80.1 dB and INL and DNL within ±1.5 LSB and ±1 LSB (full scale voltage is 1 Vp-p), when operating at 31 kHz. The incorporated imager-based temperature sensors are measured to have inaccuracies within ±0.6 °C on 4 chips, between-20 and 80 °C, when quantized by the same zoom ADC.

This paper presents a proof-of-concept CMOS image sensor (CIS) having a continuous column readout speed of 10 ​MHz. Each column readout chain, from the pixel output to the chip digital outputs, is composed of two cascade programmable gain amplifiers (PGAs) and a 10 bit 1.5 bit/stage pipelined ADC, all operating at 10 ​M samples per second. A digital background calibration method is proposed to remove the nonlinearity resulted from the capacitor mismatches in the multiplying DACs (MDACs) in each pipelined ADC stage. Measurement results from 16 columns of 10 bit single-ended pipelined ADCs show Integral Nonlinearity (INL) around 4 LSB and an Effective Number Of Bits (ENOB) of 8 (reference voltage of 1 Vpp), after being digitally calibrated. Compared to the state-of-the-art column ADCs for high speed CISs, this design has a higher speed with a figure-of-merit (FOM) of 3.2 pJ/conv. The proposed CIS's measured photoelectron transfer characteristics is shown at a column readout rate of 10 ​MHz.

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

This brief proposes employing each of the classical 4 transistor (4T) pinned photodiode (PPD) CMOS image sensor (CIS) pixels, for both imaging and temperature measurement, intended for compensating the CISs' dark current, and dark signal non-uniformity (DSNU). The proposed temperature sensors rely on the thermal behavior of MOSFETs working in subthreshold region, when biased with ratiometric currents sequentially. Without incurring any additional hardware or penalty to the CIS, they are measured to have thermal curvature errors less than ±0.3 °C and 3sigma process variations within ±1.3 °C, from 108 sensors on 4 chips, over a temperature range from -20 °C to 80 °C. Each of them consumes 576 nJ/conversion at a conversion rate of 62 samples/s, when quantized by 1 ^st-order 14 bit delta-sigma ADCs and fabricated using 0.18mu text{m} CIS technology. Experimental results show that they facilitate digital compensation for average dark current and DSNU by 78% and 20%, respectively.

This Letter presents an all-MOS self-referenced temperature sensor, intended for thermal compensation of dark current in CMOS image sensors (CIS). Its thermal sensing front-end is based on a self-biased nMOS pair working in the subthreshold region. Biased with ratiometric currents, the differential voltage output of the nMOS pair is proportional to the absolute temperature. The thermal sensing voltage is quantised by a self-referenced first-order incremental delta-sigma ADC, which obtains its reference voltage from the thermal sensing front-end. This reference voltage has been virtually attenuated, through switch capacitor charge sampling, to improve the resolution of the temperature sensor. Measured between -20 and 80°C, the proposed temperature sensor achieves an inaccuracy within ±0.55°C.

This paper proposes an array of nMOS based temperature sensors incorporated into a CMOS image sensor (CIS) for thermal compensation of the latter. Each temperature sensor features the same area as that of an image pixel. Both the temperature and the image sensors' outputs are read out by the column-level zoom ADCs, each of which offers 16 bits, with a 4-bit unit capacitor array (UCA) SAR and a 13-bit 2^nd-order incremental delta-sigma ADC (DSADC) as the first and the second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. The column zoom ADC samples twice as fast while keeping its linearity, or, expands the dynamic range by 15 dB, for the image sensors, compared to a DSADC only alternative. To digitize the temperature sensor, the proposed zoom ADC is capable of quantization errors less than 16 µV, which is equivalent to a 0.125 ⁰C resolution for a 130 µV/⁰C temperature coefficient. The proposed temperature sensor is simulated to keep its errors within ±0.21 ⁰C upon 2^nd-order curve fitting, with 3 sigma Monte Carlo inaccuracies less than ±0.74 ⁰C, between 0 and 100 ⁰C, at a power and an area of 144 µW and 121 µm², respectively, with a sampling period of 64 µs.

This paper proposes a CMOS image sensor (CIS) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method to its column-level successive approximation register (SAR) analog to digital converters (ADC), compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. Simulation results show the DEC method improves the ADC's static and dynamic linearity, eliminating its missing codes and increasing its signal to noise plus distortion ratio (SNDR) from 64.5 dB to 67.5 dB, when operating at the same sampling speed. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC, while increasing the sampling rate by 33 %. The simulated linearity of the prototype CIS is within ±0.07 %, when sampled at a column readout rate of 10 MHz.

In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18-μm, 1-poly, and 4-metal CIS technology with a pixel array of 128 × 160 is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor C _FD on the floating diffusion node, which is remnant in VM.

This paper proposes various types of on-chip smart temperature sensors, intended for thermal compensation of dark current in CMOS image sensors (CIS). It proposes four different architectures of metal-oxide-semiconductor (MOS)-based and bipolar junction transistor (BJT)-based temperature sensors inside and outside the CIS array. Both of the MOS-based temperature sensors make use of the thermal dependence of MOS transistors working in the subthreshold region with ratiometric currents and are quantized by the 14-bit first-order incremental delta-sigma analog-to-digital converters (ADCs). Fabricated using 0.18- CIS technology and measured on four chips, the proposed temperature sensors are compared, on their resolution and process variability, as well as on their effects on the neighboring image pixels implemented on the same chip. Experimental results show that the MOS-based temperature sensors inside and outside the array consume a power of 36 and 40ext{W} , respectively, both achieving 3-sigma (sigma ) inaccuracy less than ±0.75 °C on four different chips, over a temperature range from -20°C to 80 °C at a conversion time of 16 ms. The temperature sensors facilitate the digital thermal compensation of dark current in the CIS array, by at least 80%, in experiments.

This paper presents methodologies for suppressing the spatial and the temporal noise in a CMOS image sensor (CIS). First of all, it demonstrates by using a longer-length column bias transistor, both the fixed pattern noise (FPN) and temporal noise can be suppressed. Meantime, it employs column-level oversampling delta-sigma ADCs to suppress temporal noise as well as to facilitate the realization of the thermal compensation of dark signal non-uniformity (DSNU). In addition, the image pixels are re-configured as temperature sensors with inaccuracies within ±0.65 °C, between -20 and 80 °C. If the dark current and its non-uniformities are caused by thermal gradients, the obtained in-pixel thermal information can be employed to compensate for the measured dark current by 95 % and DSNU, up to 13 %. All the column-level 13 bit 2 ^nd-order incremental delta-sigma ADCs are measured with SNR around 65 dB and INL around 1.5 LSB, when tested with a -8 dB input signal and sampling at 2 MHz with an oversampling ratio (OSR) of 128, when the full scale voltage is 2 Vp-p. The 4T Pinned Photodiode (PPD) CIS is measured to have a temporal noise of 34~\mu \text{V} rms (with an OSR of 128, or, an input referred temporal noise of 0.5 e ^- rms, with a conversion gain, CG, of 73~\mu \text{V}/ \text{e}^{-} ), a column gain FPN of 0.06 %, a dynamic range (DR) of 92 dB (with OSR = 512), as well as a linearity of 1 %. It has a measured DSNU of 3.2 %, after the thermal compensation using the in-pixel temperature sensors, a dark current of 290 pA/cm ² and 15 pA/cm ², measured at 60 °C, before and after the thermal compensation, respectively.