XG
X. Ge
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In pursuit of achieving the noise condition of single-photon imaging, system-level and circuit-level innovations and optimizations for CMOS image sensor (CIS) noise reduction are called for. Stimulated by this motivation, this thesis focuses on reducing the temporal noise generated in the pixels and the readout electronics.
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In pursuit of achieving the noise condition of single-photon imaging, system-level and circuit-level innovations and optimizations for CMOS image sensor (CIS) noise reduction are called for. Stimulated by this motivation, this thesis focuses on reducing the temporal noise generated in the pixels and the readout electronics.
This paper proposes an array of nMOS based temperature sensors incorporated into a CMOS image sensor (CIS) for thermal compensation of the latter. Each temperature sensor features the same area as that of an image pixel. Both the temperature and the image sensors' outputs are read out by the column-level zoom ADCs, each of which offers 16 bits, with a 4-bit unit capacitor array (UCA) SAR and a 13-bit 2nd-order incremental delta-sigma ADC (DSADC) as the first and the second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. The column zoom ADC samples twice as fast while keeping its linearity, or, expands the dynamic range by 15 dB, for the image sensors, compared to a DSADC only alternative. To digitize the temperature sensor, the proposed zoom ADC is capable of quantization errors less than 16 µV, which is equivalent to a 0.125 0C resolution for a 130 µV/0C temperature coefficient. The proposed temperature sensor is simulated to keep its errors within ±0.21 0C upon 2nd-order curve fitting, with 3 sigma Monte Carlo inaccuracies less than ±0.74 0C, between 0 and 100 0C, at a power and an area of 144 µW and 121 µm2, respectively, with a sampling period of 64 µs.
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This paper proposes an array of nMOS based temperature sensors incorporated into a CMOS image sensor (CIS) for thermal compensation of the latter. Each temperature sensor features the same area as that of an image pixel. Both the temperature and the image sensors' outputs are read out by the column-level zoom ADCs, each of which offers 16 bits, with a 4-bit unit capacitor array (UCA) SAR and a 13-bit 2nd-order incremental delta-sigma ADC (DSADC) as the first and the second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. The column zoom ADC samples twice as fast while keeping its linearity, or, expands the dynamic range by 15 dB, for the image sensors, compared to a DSADC only alternative. To digitize the temperature sensor, the proposed zoom ADC is capable of quantization errors less than 16 µV, which is equivalent to a 0.125 0C resolution for a 130 µV/0C temperature coefficient. The proposed temperature sensor is simulated to keep its errors within ±0.21 0C upon 2nd-order curve fitting, with 3 sigma Monte Carlo inaccuracies less than ±0.74 0C, between 0 and 100 0C, at a power and an area of 144 µW and 121 µm2, respectively, with a sampling period of 64 µs.
This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.
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This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.
A deep subelectron temporal noise CMOS image sensor (CIS) with a Gm-cell based pixel and a correlated-double charge-domain sampling technique has been developed for photon-starved imaging applications. With the proposed technique, the CIS, which is implemented in a standard 0.18-μm CIS process, features pixel-level amplification and achieves an input-referred noise of 0.5 e−rms with a correlated double sampling period of 5μs and a row read-out time of 10 μs. The proposed structurealso realizes a variable conversion gain (CG) with a period-controlled method. This enables the read-out path CG and the noise-equivalent number of electrons to be programmable according to the application without any change in hardware. The experiments show that the measured CG can be tuned from 50 μV/e- to 1.6 mV/e- with a charging period from 100 ns to 4μs. The measured characteristics of the prototype CIS are in a good agreement with expectations, demonstrating the effectiveness of the proposed techniques.
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A deep subelectron temporal noise CMOS image sensor (CIS) with a Gm-cell based pixel and a correlated-double charge-domain sampling technique has been developed for photon-starved imaging applications. With the proposed technique, the CIS, which is implemented in a standard 0.18-μm CIS process, features pixel-level amplification and achieves an input-referred noise of 0.5 e−rms with a correlated double sampling period of 5μs and a row read-out time of 10 μs. The proposed structurealso realizes a variable conversion gain (CG) with a period-controlled method. This enables the read-out path CG and the noise-equivalent number of electrons to be programmable according to the application without any change in hardware. The experiments show that the measured CG can be tuned from 50 μV/e- to 1.6 mV/e- with a charging period from 100 ns to 4μs. The measured characteristics of the prototype CIS are in a good agreement with expectations, demonstrating the effectiveness of the proposed techniques.
This paper presents an analysis and calibration of process variations for an array of temperature sensors, which are incorporated into a CMOS image sensor chip. Making use of the experimental results of more than 500 temperature sensors implemented on the same chip, the proposed calibration method has removed their process variations from 14.3 % to 2.5 % (3 sigma).
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This paper presents an analysis and calibration of process variations for an array of temperature sensors, which are incorporated into a CMOS image sensor chip. Making use of the experimental results of more than 500 temperature sensors implemented on the same chip, the proposed calibration method has removed their process variations from 14.3 % to 2.5 % (3 sigma).
This paper presents a noise analysis and noise measurementsof n-type and p-type pixels with correlated multiple sampling(CMS) technique. The output noise power spectral density (PSD)of both pixel types with different CMS noise reduction factors havebeen simulated and calculated in the spectral domain. Forvalidation, two groups of test pixel have been fabricated with astate-of-the-art n-type and p-type CMOS image sensor (CIS)technology. The calculated and the measured noise results withCMS show a good agreement. Measurement results also show thatthe n-type and p-type pixels reach a 1.1 e- and 0.88 h+ inputreferredtemporal noise respectively with a board-level 64 timesdigital CMS and ×6 analog gain.
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This paper presents a noise analysis and noise measurementsof n-type and p-type pixels with correlated multiple sampling(CMS) technique. The output noise power spectral density (PSD)of both pixel types with different CMS noise reduction factors havebeen simulated and calculated in the spectral domain. Forvalidation, two groups of test pixel have been fabricated with astate-of-the-art n-type and p-type CMOS image sensor (CIS)technology. The calculated and the measured noise results withCMS show a good agreement. Measurement results also show thatthe n-type and p-type pixels reach a 1.1 e- and 0.88 h+ inputreferredtemporal noise respectively with a board-level 64 timesdigital CMS and ×6 analog gain.
This paper presents a CMOS image sensor with in-pixel nearly unity-gain pMOS transistor based source followers and optimized column-parallel amplifiers. The prototype sensor has been fabricated in a 0.18 μm CMOS process. By eliminating the body effect of the source follower transistor, the voltage gain for the pixel-level readout circuitry approaches unity. The use of a single-ended common-source cascode amplifier with ground rail regulation improves the PSRR of the column-parallel analog front-end circuitry and further the noise performance. Electrical characterization results show that the proposed pixel improves the conversion gain after the in-pixel source follower by 42% compared to that of the conventional structure. The prototype sensor with proposed readout architecture reaches a 1.1e- input-referred temporal noise with a column-level ×16 analog gain.
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This paper presents a CMOS image sensor with in-pixel nearly unity-gain pMOS transistor based source followers and optimized column-parallel amplifiers. The prototype sensor has been fabricated in a 0.18 μm CMOS process. By eliminating the body effect of the source follower transistor, the voltage gain for the pixel-level readout circuitry approaches unity. The use of a single-ended common-source cascode amplifier with ground rail regulation improves the PSRR of the column-parallel analog front-end circuitry and further the noise performance. Electrical characterization results show that the proposed pixel improves the conversion gain after the in-pixel source follower by 42% compared to that of the conventional structure. The prototype sensor with proposed readout architecture reaches a 1.1e- input-referred temporal noise with a column-level ×16 analog gain.