This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.@en

This brief proposes employing each of the classical 4 transistor (4T) pinned photodiode (PPD) CMOS image sensor (CIS) pixels, for both imaging and temperature measurement, intended for compensating the CISs' dark current, and dark signal non-uniformity (DSNU). The proposed temperature sensors rely on the thermal behavior of MOSFETs working in subthreshold region, when biased with ratiometric currents sequentially. Without incurring any additional hardware or penalty to the CIS, they are measured to have thermal curvature errors less than ±0.3 °C and 3sigma process variations within ±1.3 °C, from 108 sensors on 4 chips, over a temperature range from -20 °C to 80 °C. Each of them consumes 576 nJ/conversion at a conversion rate of 62 samples/s, when quantized by 1 st-order 14 bit delta-sigma ADCs and fabricated using 0.18mu text{m} CIS technology. Experimental results show that they facilitate digital compensation for average dark current and DSNU by 78% and 20%, respectively. @en

This paper presents a CMOS image sensor (CIS) with a zoom ADC, to quantize in-pixel temperature sensors, as well as for faster readout speed of the image pixels while maintaining low quantization noise. The proposed 15 bit zoom ADC has a 4 bit Unit Capacitor Array (UCA) SAR and a 13 bit incremental 2nd-order delta-sigma ADC (DSADC), as its first and second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. Measurement results on 4 chips show the proposed zoom ADC could operate at least twice as fast, when maintaining the same signal-to-noise ratio (SNR), or improve its SNR by 9 dB, when maintaining its sampling speed, compared to a DSADC only alternative. The proposed 15 bit ADC is measured a SNR of 80.1 dB and INL and DNL within ±1.5 LSB and ±1 LSB (full scale voltage is 1 Vp-p), when operating at 31 kHz. The incorporated imager-based temperature sensors are measured to have inaccuracies within ±0.6 °C on 4 chips, between-20 and 80 °C, when quantized by the same zoom ADC.@en

This paper presents a proof-of-concept CMOS image sensor (CIS) having a continuous column readout speed of 10 ​MHz. Each column readout chain, from the pixel output to the chip digital outputs, is composed of two cascade programmable gain amplifiers (PGAs) and a 10 bit 1.5 bit/stage pipelined ADC, all operating at 10 ​M samples per second. A digital background calibration method is proposed to remove the nonlinearity resulted from the capacitor mismatches in the multiplying DACs (MDACs) in each pipelined ADC stage. Measurement results from 16 columns of 10 bit single-ended pipelined ADCs show Integral Nonlinearity (INL) around 4 LSB and an Effective Number Of Bits (ENOB) of 8 (reference voltage of 1 Vpp), after being digitally calibrated. Compared to the state-of-the-art column ADCs for high speed CISs, this design has a higher speed with a figure-of-merit (FOM) of 3.2 pJ/conv. The proposed CIS's measured photoelectron transfer characteristics is shown at a column readout rate of 10 ​MHz.

@en

This paper analyzes and compensates for process and temperature dependency among a (Complementary Metal Oxide Semiconductor) CMOS image sensor (CIS) array. Both the analysis and compensation are supported with experimental results on the CIS’s dark current, dark signal non-uniformity (DSNU), and conversion gain (CG). To model and to compensate for process variations, process sensors based on pixel source follower (SF)’s transconductance g m,SF have been proposed to model and to be compared against the measurement results of SF gain A SF . In addition, A SF ’s thermal dependency has been analyzed in detail. To provide thermal information required for temperature compensation, six scattered bipolar junction transistor (BJT)-based temperature sensors replace six image pixels inside the array. They are measured to have an untrimmed inaccuracy within ±0.5 ⁰C. Dark signal and CG’s thermal dependencies are compensated using the on-chip temperature sensors by at least 79% and 87%, respectively. @en

This paper proposes an array of nMOS based temperature sensors incorporated into a CMOS image sensor (CIS) for thermal compensation of the latter. Each temperature sensor features the same area as that of an image pixel. Both the temperature and the image sensors' outputs are read out by the column-level zoom ADCs, each of which offers 16 bits, with a 4-bit unit capacitor array (UCA) SAR and a 13-bit 2nd-order incremental delta-sigma ADC (DSADC) as the first and the second stage, respectively. The proposed UCA with improved switching and decoding technique minimizes capacitor area and switching energy, by 50 % and 75 %, respectively, compared to a conventional binary weight array (BWA) counterpart. The column zoom ADC samples twice as fast while keeping its linearity, or, expands the dynamic range by 15 dB, for the image sensors, compared to a DSADC only alternative. To digitize the temperature sensor, the proposed zoom ADC is capable of quantization errors less than 16 µV, which is equivalent to a 0.125 0C resolution for a 130 µV/0C temperature coefficient. The proposed temperature sensor is simulated to keep its errors within ±0.21 0C upon 2nd-order curve fitting, with 3 sigma Monte Carlo inaccuracies less than ±0.74 0C, between 0 and 100 0C, at a power and an area of 144 µW and 121 µm2, respectively, with a sampling period of 64 µs.@en

This paper proposes a CMOS image sensor (CIS) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method to its column-level successive approximation register (SAR) analog to digital converters (ADC), compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. Simulation results show the DEC method improves the ADC's static and dynamic linearity, eliminating its missing codes and increasing its signal to noise plus distortion ratio (SNDR) from 64.5 dB to 67.5 dB, when operating at the same sampling speed. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC, while increasing the sampling rate by 33 %. The simulated linearity of the prototype CIS is within ±0.07 %, when sampled at a column readout rate of 10 MHz.

@en

This paper proposes various types of on-chip smart temperature sensors, intended for thermal compensation of dark current in CMOS image sensors (CIS). It proposes four different architectures of metal-oxide-semiconductor (MOS)-based and bipolar junction transistor (BJT)-based temperature sensors inside and outside the CIS array. Both of the MOS-based temperature sensors make use of the thermal dependence of MOS transistors working in the subthreshold region with ratiometric currents and are quantized by the 14-bit first-order incremental delta-sigma analog-to-digital converters (ADCs). Fabricated using 0.18- CIS technology and measured on four chips, the proposed temperature sensors are compared, on their resolution and process variability, as well as on their effects on the neighboring image pixels implemented on the same chip. Experimental results show that the MOS-based temperature sensors inside and outside the array consume a power of 36 and 40ext{W} , respectively, both achieving 3-sigma (sigma ) inaccuracy less than ±0.75 °C on four different chips, over a temperature range from -20°C to 80 °C at a conversion time of 16 ms. The temperature sensors facilitate the digital thermal compensation of dark current in the CIS array, by at least 80%, in experiments.@en

This Letter presents an all-MOS self-referenced temperature sensor, intended for thermal compensation of dark current in CMOS image sensors (CIS). Its thermal sensing front-end is based on a self-biased nMOS pair working in the subthreshold region. Biased with ratiometric currents, the differential voltage output of the nMOS pair is proportional to the absolute temperature. The thermal sensing voltage is quantised by a self-referenced first-order incremental delta-sigma ADC, which obtains its reference voltage from the thermal sensing front-end. This reference voltage has been virtually attenuated, through switch capacitor charge sampling, to improve the resolution of the temperature sensor. Measured between -20 and 80°C, the proposed temperature sensor achieves an inaccuracy within ±0.55°C.

@en

In this work, a novel approach for measuring relative temperature variations across the active area of a CMOS image sensor itself is presented. 555 Image pixels have been replaced by temperature sensors pixels (Tixels) in the same pixel array layer. Both sensors, pixels and Tixels, utilize the same readout structure to obtain the data. This approach of measuring temperature variations in the pixel array can be used to compensate for dark signal non-uniformity. Measurements of dark current and temperature have been performed in a temperature range of −40 and 90 °C. Results show that pixels and Tixels are working by using the same readout system based on source followers and column amplifiers. The average dark current of the image sensor increases with temperature in the temperature range of −40 and 60 °C, and at the same time, Tixels show high linear response, having a temperature error less than 0.6 °C after a 1st order best curve fitting.@en

In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of pixels and temperature sensors pixels (=Tixels). The size of the Tixels is 11 μm × 11 μm. Pixels and Tixels are placed next to each other in the active imaging array and use the same readout circuits. The design and the first measurements of the combined image-temperature sensor are presented. @en

This paper presents an analysis and calibration of process variations for an array of temperature sensors, which are incorporated into a CMOS image sensor chip. Making use of the experimental results of more than 500 temperature sensors implemented on the same chip, the proposed calibration method has removed their process variations from 14.3 % to 2.5 % (3 sigma).@en